Abstract: A display panel, a display device, and a driving method thereof are provided. A light-reflecting layer is disposed under a light-emitting layer of the display panel. When the display panel is under strong light, the light-emitting layer does not work, and the light-reflecting layer reflects natural light to achieve a full-color display. When the display panel is in low light or darkness, the light-emitting layer works, and the light-reflecting layer reflects the light emitted by the light-emitting layer to reduce a working intensity of the light-emitting layer and achieves the full-color display, thereby improving service life and visual effect of organic light emitting diodes (OLEDs).

Abstract: A method of manufacturing a display panel includes fabricating a display portion on a glass substrate; forming a barrier layer on the glass substrate outside the display portion; forming an encapsulation film on the barrier layer and the display portion; and obtaining a panel area by removing the barrier layer and the encapsulation film outside a predetermined limited area on the glass substrate. The predetermined limited area corresponds to the display portion.

Abstract: A semiconductor structure includes a substrate, a first epitaxial layer, a second epitaxial layer, and a transistor. The substrate includes a first pyramid protrusion, a second pyramid protrusion, a third pyramid protrusion, and a fourth pyramid protrusion. The first and second pyramid protrusions are arranged along a first direction, the second and fourth pyramid protrusions are arranged along the first direction, and the first and third pyramid protrusions are arranged along a second direction crossing the first direction. The first epitaxial layer is over the substrate and in contact with the first, second, third, and fourth pyramid protrusions. The second epitaxial layer is over the first epitaxial layer. The transistor is over the second epitaxial layer.

Abstract: A semiconductor device includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a fifth semiconductor region, a first gate electrode, and a second gate electrode. The first gate electrode faces the second semiconductor region via a first insulating film. The second gate electrode faces the second semiconductor region via a second insulating film and faces the second electrode via a third insulating film contacting the second insulating film. The fifth semiconductor region includes a boundary portion that electrically contacts the second electrode. A distance between an upper surface of the fourth semiconductor region and the first electrode is greater than a distance between the boundary portion and the first electrode.

Abstract: A semiconductor device includes first and second source/drain regions, a core channel region, a barrier layer, a shell, and a gate stack. The core channel region is between the first and second source/drain regions and is doped with first dopants. The barrier layer is between the core channel region and the second source/drain region and is doped with second dopants. The shell is over the core channel region and the barrier layer. The gate stack is over the shell.

Abstract: A method of producing a silicon carbide (SiC) device includes: forming a stripe-shaped trench gate structure that extends from a first surface of a SiC body into the SiC body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; forming at least one source region of a first conductivity type; and forming a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. Forming the shielding region includes: forming a deep shielding portion; and forming a top shielding portion between the first surface and the deep shielding portion, the top shielding portion being in contact with the first bottom edge.

Abstract: A display device includes a first electrode, a second electrode spaced apart from the first electrode and facing the first electrode, a first insulating layer disposed to at least partially cover the first electrode and the second electrode, a second insulating layer disposed on at least a part of the first insulating layer, and a light-emitting element disposed on the second insulating layer between the first electrode and the second electrode, wherein at least a part of a lower surface of the light-emitting element is chemically bonded to the second insulating layer.

Abstract: An IGBT capable of handling high-speed switching while reducing a leakage current of a semiconductor device including the IGBT is provided. The semiconductor device according to one embodiment includes an IGBT including a p-type collector layer on a back surface of a silicon substrate and a dislocation suppressing layer for forming a hetero junction with silicon in the p-type collector layer. The dislocation suppressing layer includes a silicon germanium (SiGe) layer.

Abstract: A silicon carbide device includes a transistor cell with a source region and a gate electrode. The source region is formed in a silicon carbide body and has a first conductivity type. A first low-resistive ohmic path electrically connects the source region and a doped region of a second conductivity type. The doped region and a floating well of the first conductivity type form a pn junction. A first clamp region having the second conductivity type extends into the floating well. A second low-resistive ohmic path electrically connects the first clamp region and the gate electrode.

Abstract: A feeder design is manufactured as a structure in a SiC semiconductor material comprising at least two p-type grids in an n-type SiC material (3), comprising at least one epitaxially grown p-type region, wherein an Ohmic contact is applied on the at least one epitaxially grown p-type region, wherein an epitaxially grown n-type layer is applied on at least a part of the at least two p-type grids and the n-type SiC material (3) wherein the at least two p-type grids (4, 5) are applied in at least a first and a second regions at least close to the at least first and second corners respectively and that there is a region in the n-type SiC material (3) between the first and a second regions without any grids.

Abstract: Provided is a semiconductor device, comprising a semiconductor substrate; and an emitter electrode provided above an upper surface of the semiconductor substrate; wherein the semiconductor substrate has: a first conductive type drift region; a second conductive type base region provided between the drift region and the upper surface of the semiconductor substrate; a second conductive type contact region with a higher doping concentration than the base region, which is provided between the base region and the upper surface of the semiconductor substrate; a trench contact of a conductive material provided to connect to the emitter electrode and penetrate the contact region; and a second conductive type high-concentration plug region with a higher doping concentration than the contact region, which is provided in contact with a bottom portion of the trench contact.

Abstract: A display device includes: a base substrate; a TFT layer including a plurality of pixel circuits arranged; and a light-emitting element layer. Each of the plurality of pixel circuits includes: a TFT including a semiconductor layer, a gate insulating film, and a gate electrode; and a capacitor including the gate electrode, a first inorganic insulating film, and a capacitive electrode. The capacitive electrode extends all around a perimeter of the gate electrode and extends to an outside of the perimeter. An angle formed between an upper surface of the base substrate and at least a part of an end surface in a circumferential direction of the gate electrode not overlapping the semiconductor layer in the plan view is greater than an angle formed between the upper surface of the base substrate and an end surface of the gate electrode overlapping the semiconductor layer in the plan view.

Abstract: A method of reducing stray coupling in a qubit array, includes turning ON a first coupler between a first qubit and second qubit of the qubit array by providing a pulse having a first amplitude to the first coupler. A stray coupling between the first coupler and a spectator qubit is reduced by turning ON a second coupler coupled to the spectator qubit, by providing a compensation pulse having a second amplitude, to the second coupler, based on the pulse having the first amplitude.

Abstract: The present application provides a display panel and a display device. The display panel includes a first wiring layer connected between a first pixel driving circuit and a first light-emitting device; a signal wiring layer electrically connected to the first pixel driving circuit and partially overlapping the first wiring layer; and a capacitive barrier layer disposed between the first wiring layer and the signal wiring layer and including at least one organic insulating layer, so as to improve the display effect of the display light-transmitting area through the capacitive barrier layer.

Abstract: An 8-inch SiC single crystal substrate of an embodiment has a diameter in a range of 195 mm to 205 mm, a thickness in a range of 300 ?m to 650 ?m, a SORI of 50 ?m or less, and an in-plane variation of the thickness of the substrate, which is the difference between the maximum and minimum substrate thickness at the center of the substrate and four points on the circumference of a circle having a radius half the radius of the substrate, is 1.5 ?m or less.

Abstract: A lighting device is specified. The lighting device comprises a phosphor having the general molecular formula (MA)a(MB)b(MC)c(MD)d(TA)e(TB)f(TC)g(TD)h(TE)i(TF)j(XA)k(XB)l(XC)m(XD)n:E. In this case, MA is selected from a group of monovalent metals, MB is selected from a group of divalent metals, MC is selected from a group of trivalent metals, MD is selected from a group of tetravalent metals, TA is selected from a group of monovalent metals, TB is selected from a group of divalent metals, TC is selected from a group of trivalent metals, TD is selected from a group of tetravalent metals, TE is selected from a group of pentavalent elements, TF is selected from a group of hexavalent elements, XA is selected from a group of elements which comprises halogens, XB is selected from a group of elements which comprises O, S and combinations thereof, XC=N and XD=C and E=Eu, Ce, Yb and/or Mn. The following furthermore hold true: a+b+c+d=t; e+f+g+h+i+j=u; k+l+m+n=v; a+2b+3c+4d+e+2f+3g+4h+5i+6j?k?2l?3m?4n=w; 0.8?t?1; ?3.

Abstract: A radiation-emitting semiconductor device (1) is specified, comprising a semiconductor body (2) having an active region (20) provided for generating radiation, a carrier (3) on which the semiconductor body is arranged and an optical element (4), wherein the optical element is attached to the semiconductor body by a direct bonding connection. Furthermore, a method for producing of radiation-emitting semiconductor devices is specified.

Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to increase thermal stability. In some embodiments, a capping layer that is a conductive metal nitride such as MoN contacts an opposite surface of the Hk enhancing layer with respect to the first interface to reduce interdiffusion of oxygen and nitrogen compared with a TiN capping layer and maintain an acceptable resistance×area (RA) product. In other embodiments, the capping layer may comprise an insulating nitride such as AlN that is alloyed with a conductive metal to minimize RA. Furthermore, a metallic buffer layer may be inserted between the capping layer and Hk enhancing layer. As a result, electrical shorts are reduced and the magnetoresistive ratio is increased.

Abstract: An integrated device includes at least one MOS transistor having a plurality of cells. In each of one or more of the cells a disabling structure is provided. The disabling structure is configured to be in a non-conductive condition when the MOS transistor is switched on in response to a control voltage comprised between a threshold voltage of the MOS transistor and an intervention voltage of the disabling structure, or to be in a conductive condition otherwise. A system comprising at least one integrated device as above is also proposed. Moreover, a corresponding process for manufacturing this integrated device is proposed.

Abstract: A semiconductor device for reducing a switching loss includes a drain metal. A silicon substrate of a first conductive type is provided on the drain metal. An epitaxial layer of the first conductive type is provided on the silicon substrate of the first conductive type. A pillar of the first conductive type and a pillar of a second conductive type are arranged in the epitaxial layer of the first conductive type. A body region of the second conductive type is provided on a surface of each pillar. A heavily doped source region of the first conductive type and a heavily doped source region of the second conductive type are arranged in the body region of the second conductive type. A gate trench is formed in the pillar of the first conductive type. Discrete gate polycrystalline silicon is provided in the gate trench.