Abstract: A quantum dot includes a core-shell structure including a core including a first semiconductor nanocrystal and a shell disposed on the core, and including a material at least two different halogens, and the quantum dot does not include cadmium.

Abstract: A memory device includes: a first conductor extending in parallel with a first axis; a first selector material comprising a first portion that extends along a first sidewall of the first conductor; a second selector material comprising a first portion that extends along the first sidewall of the first conductor; a first variable resistive material comprising a portion that extends along the first sidewall of the first conductor; and a second conductor extending in parallel with a second axis substantially perpendicular to the first axis, wherein the first portion of the first selector material, the first portion of the second selector material, and the portion of the first variable resistive material are arranged along a first direction in parallel with a third axis substantially perpendicular to the first axis and second axis.

Abstract: Disclosed is a display apparatus. The display apparatus includes a substrate including a first subpixel, a second subpixel, and a third subpixel. A bottom electrode is on the substrate. A light emitting layer is on the bottom electrode, and a top electrode is on the light emitting layer. Each of the first subpixel, the second subpixel, and the third subpixel includes a first mode pixel having a first viewing angle and a second mode pixel having a second viewing angle that is less than the first viewing angle.

Abstract: The present inventive concept provides a moisture prevention film including: a first moisture prevention film; a second moisture prevention film formed on the first moisture prevention film; and a third moisture prevention film formed on the second moisture prevention film, wherein a concentration of oxygen (O) of the second moisture prevention film is higher than a concentration of oxygen of each of the first moisture prevention film and the third moisture prevention film, a method of manufacturing the moisture prevention film, and an organic light emitting device including the moisture prevention film.

Abstract: A semiconductor device includes a stack structure including alternately stacked interlayer insulating layers and electrode patterns. The semiconductor device also includes a plurality of contact plugs connected to the electrode patterns. The semiconductor device further includes a supporting structure penetrating the stack structure between two adjacent contact plugs of the plurality of contact plugs, wherein the supporting structure has a cross section extending in a zigzag shape.

Abstract: A circuit test structure including an interposer for electrically connection to a chip, wherein the interposer includes a conductive line, and the conductive line traces a perimeter of the interposer. The circuit test structure further includes at least three electrical connections to the conductive line. The circuit test structure further includes a testing site. The circuit test structure further includes a through substrate via (TSV) connecting the testing site to the conductive line.

Abstract: A display device according to an exemplary embodiment includes: a first substrate; first data pads that are disposed in a first row extending along a first direction on the first substrate, second data pads that are disposed in a second row extending along the first direction on the first substrate, gate pads that are disposed in the first row and are not disposed in the second row on the first substrate, data lines that are connected with the first data pads and the second data pads on the first substrate, and control signal lines that are connected the gate pads, wherein the control signal lines extend in a side area of the second data pads from the gate pads.

Abstract: A display panel includes a substrate having an opening area, and a display area at least partially surrounding the opening area. Display elements are arranged in the display area. The display elements includes a pixel electrode, an opposite electrode, and an intermediate layer interposed therebetween. A multilayer film includes a first insulating layer between the substrate and the pixel electrode and a second insulating layer, of a different material, on the first insulating layer. A thin film encapsulation layer covers the display elements and includes at least one organic encapsulation layer and at least one inorganic encapsulation layer. The multilayer film includes a first groove disposed between the opening area and the display area. The first groove has an undercut structure in which a lower width of the first groove is greater than an upper width of the first groove.

Abstract: A display apparatus includes: a first thin-film transistor (TFT) including a first semiconductor layer including a silicon semiconductor; a second TFT including a second semiconductor layer including an oxide semiconductor; a first shielding layer configured to overlap the first TFT and positioned between a substrate and the first TFT; and a second shielding layer configured to overlap the second TFT and positioned between the substrate and the second TFT.

Abstract: A semiconductor device includes a semiconductor part between first and second electrodes, first and second control electrodes between the semiconductor part and the second electrode. The semiconductor part includes a first region and a second region around the first region. The semiconductor part includes first and third layers of a first conductivity type and second layers of a second conductivity type. The second layers are provided between the first layer and the second electrode. A second layer faces the first control electrode in the second region. Another second layer faces the second control electrode in the second region. A third layer is provided between the second layer and the second electrode. Another third layer is provided between another second layer and the second electrode. The second layer includes a second conductivity type impurity with a concentration lower than that of a second conductivity type impurity in another second layer.

Abstract: In accordance with an embodiment of the present invention, a method of making a semiconductor device includes simultaneously etching a semiconductor layer and a conductive layer to form a self-aligned diode region disposed on an insulating layer, where the semiconductor layer has a first conductivity type. The method further includes etching through first openings of a mask layer to form first implantation surfaces on the semiconductor layer and to form a plurality of projecting regions including conductive material of the conductive layer over the semiconductor layer. The method further includes using the plurality of projecting regions as a part of a first implantation mask, performing a first implantation of dopants having a second conductivity type into the semiconductor layer, to form a sequence of PN junctions forming diodes in the semiconductor layer. The diodes vertically extend from an upper surface of the semiconductor layer to the insulating layer.

Abstract: A semiconductor memory device includes a first insulating layer over a semiconductor substrate, a metal layer, an adhesive layer on a first region of the metal layer, a conductive layer on a second region of the metal layer and on the adhesive layer, a second insulating layer on the conductive layer, a plurality of wiring layers that are separated from each other and are stacked above the second insulating layer, a semiconductor layer that extends in a first direction perpendicular to the semiconductor substrate and includes a bottom surface connected to the conductive layer, a storage portion disposed between at least one of the plurality of wiring layers and the semiconductor layer, and a slit that extends in the first direction, includes aside surface in contact with the plurality of wiring layers and a bottom surface reaching the conductive layer, and is filled with an insulating material.

Abstract: An adhesive composition comprising (a) a (meth)acrylic polymer, (b) a compound having at least two (meth)acryloyl groups, (c) a polymerization initiator and (d) a filler.

Abstract: A stacked quantum computing device including: a first chip including a superconducting qubit, where the superconducting qubit includes a superconducting quantum interference device (SQUID) region, a control region, and a readout region, and a second chip bonded to the first chip, where the second chip includes a first control element overlapping with the SQUID region, a second control element displaced laterally from the control region and without overlapping the control region, and a readout device overlapping the readout region.

Abstract: A memory device is disclosed. The memory device includes a bottom contact, and a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a top contact on the top electrode, and a first barrier layer, including a first oxide material and a second oxide material, where the first oxide material is different from the second oxide material, and where the first barrier layer is between one of A) the memory layer and the bottom contact, and B) the top electrode and the top contact, where the first barrier layer is configured to substantially prevent the conduction of ions or vacancies therethrough.

Abstract: A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.

Abstract: A monitoring system includes a shoe and a sole integrated into the shoe. The monitoring system also includes a connection mechanism attached to an underside of the sole and is shaped to connect the sole to a pedal. A pressure sensor is incorporated into the shoe that senses a force exerted on the pedal when the shoe is connected to the pedal through the connection mechanism.

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

Abstract: A replacement fin in a heterogeneous FinFET transistor in which source and drain regions are grown in corresponding trenches that extend into a sub-fin region. This depth of the epitaxial source/drain regions, in combination with the selected materials, can reduce off-state leakage while also keeping high defect density portions out of the active portions of the source and drain. In one embodiment, materials are selected for the source and drain regions that have an energy band offset from the material selected for the substrate. This band offset between the source/drain material can further reduce sub-fin leakage.

Abstract: Fin-based thin film resistors, and methods of fabricating fin-based thin film resistors, are described. In an example, an integrated circuit structure includes a fin protruding through a trench isolation region above a substrate. The fin includes a semiconductor material and has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. An isolation layer is conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A resistor layer is conformal with the isolation layer conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A first anode cathode electrode is electrically connected to the resistor layer. A second anode or cathode electrode is electrically connected to the resistor layer.