Patents Examined by Igwe U. Anya
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Patent number: 11171060Abstract: A semiconductor device and a method of forming a semiconductor device. The semiconductor device includes a first raised feature in a n-type channel field effect transistor (NFET) region on a substrate, a first doped epitaxial semiconductor material grown on the first raised feature, a first metal contact on the first doped epitaxial semiconductor material, a first metal nitride on the first metal contact, and a first ruthenium (Ru) metal plug on the first metal nitride. The device further includes a second raised feature in a p-type channel field effect transistor (PFET) region on the substrate, a second doped epitaxial semiconductor material grown on the second raised feature, a second metal contact on the second doped epitaxial semiconductor material, a second metal nitride on the second metal contact, and a second ruthenium (Ru) metal plug on the second metal nitride.Type: GrantFiled: February 27, 2020Date of Patent: November 9, 2021Assignee: Tokyo Electron LimitedInventors: Hiroaki Niimi, Gyanaranjan Pattanaik
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Patent number: 11158706Abstract: A feeder design is manufactured as a structure in a SiC semiconductor material comprising at least two p-type grids in an n-type SiC material, comprising at least one epitaxially grown p-type region, wherein an Ohmic contact is applied on the at least one epitaxially grown p-type region, wherein an epitaxially grown n-type layer is applied on at least a part of the at least two p-type grids and the n-type SiC material wherein the at least two p-type grids are applied in at least a first and a second regions at least close to the at least first and second corners respectively and that there is a region in the n-type SiC material between the first and a second regions without any grids.Type: GrantFiled: September 14, 2018Date of Patent: October 26, 2021Assignee: II-VI Delaware, IncInventors: Hossein Elahipanah, Nicolas Thierry-Jebali, Adolf Schöner, Sergey Reshanov
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Patent number: 11152502Abstract: The nitride semiconductor device includes: a nitride semiconductor layer; a first conductivity type source region provided on a surface of the nitride semiconductor layer; a second conductivity type well region provided in the nitride semiconductor layer and adjacent to the source region in a first direction parallel to the surface and in a second direction intersecting with the first direction; a trench located on the opposite side of the source region with the well region sandwiched therebetween in the first direction; a first conductivity type impurity region located between the well region and the trench; an insulating film provided on a bottom surface of the trench; a gate insulating film provided on the well region; and a gate electrode provided from on the insulating film to on the gate insulating film. A thickness of the insulating film is larger than a thickness of the gate insulating film.Type: GrantFiled: February 25, 2020Date of Patent: October 19, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Katsunori Ueno
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Patent number: 11149196Abstract: An organic luminescent material suitable for color conversion material used for a liquid crystal display or LED lighting, excellent in luminous efficiency and durability, to which a pyrromethene-boron complex or a color conversion composition containing the pyrromethene-boron complex contributes, is provided.Type: GrantFiled: July 22, 2020Date of Patent: October 19, 2021Assignee: TORAY INDUSTRIES, INC.Inventors: Yasunori Ichihashi, Masaaki Umehara, Hirotoshi Sakaino, Daisaku Tanaka
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Patent number: 11145813Abstract: A conductive microstud is formed in a recess of an insulator layer formed on the substrate. A bottom pedestal is formed on a top surface of the microstud. The material used for the bottom pedestal has a lower electrochemical voltage than a material used for the microstud. A top pedestal is formed on a top surface of the bottom pedestal. The top surface of at least one of the bottom pedestal and top pedestal is planarized. A conductive layer is formed on a top surface of the top pedestal. Next, a conical structure is formed. The conical structure is comprised of at least the conductive layer and a top portion of the top pedestal.Type: GrantFiled: January 3, 2020Date of Patent: October 12, 2021Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Theodorus E Standaert, Daniel C Edelstein
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Patent number: 11139416Abstract: A method for manufacturing an LED display device and an LED display device are provided. The method includes following operations. An LED array substrate and a conversion plate are provided. The LED array substrate includes a driving layer, a plurality of LED chips arranged in an array on a side of the LED array substrate having the driving layer. The conversion plate includes a substrate and a plurality of light conversion blocks, the plurality of light conversion blocks are spaced apart from each other and arranged on the substrate. A side of the conversion plate having the light conversion blocks is adhered with a side of the LED array substrate having the LED chips correspondingly, such that the light conversion blocks are arranged on corresponded top surfaces of the LED chips. The substrate is removed.Type: GrantFiled: January 27, 2020Date of Patent: October 5, 2021Assignee: CHENGDU VISTAR OPTOELECTRONICS CO., LTD.Inventors: Dong Wei, Xiaolong Yang, Jiantai Wang, Huashan Chen
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Patent number: 11139291Abstract: A semiconductor device is provided, including a semiconductor substrate, wherein the semiconductor substrate has: a diode region; a transistor region; and a boundary region that is positioned between the diode region and the transistor region, the boundary region includes a defect region that is provided: at a predetermined depth position on a front surface-side of the semiconductor substrate; and to extend from an end portion of the boundary region adjacent to the diode region toward the transistor region, at least part of the boundary region does not include a first conductivity-type emitter region exposed on a front surface of the semiconductor substrate, and the transistor region does not have the defect region below a mesa portion that is sandwiched by two adjacent trench portions, and closest to the boundary region among the mesa portions having the emitter region.Type: GrantFiled: November 29, 2019Date of Patent: October 5, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takahiro Tamura, Yuichi Onozawa, Misaki Takahashi, Kaname Mitsuzuka, Daisuke Ozaki, Akinori Kanetake
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Patent number: 11139213Abstract: Methods for 3D fabrication of source/drain regions in different stacks of 3D transistors in which multiple planes are fabricated simultaneously are described. The methods allow any sequence of 3D source/drains to be made to customize the logic layout for a given 3D logic circuit or design. Examples are described of forming a stacked SRAM device, a dual stacked SRAM device and a plurality of stacked inverters based on NMOS and PMOS field effect transistors.Type: GrantFiled: April 10, 2020Date of Patent: October 5, 2021Assignee: Tokyo Electron LimitedInventors: Mark I. Gardner, H. Jim Fulford
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Patent number: 11133464Abstract: An electronic device is disclosed. The electronic device includes a conductor, and a conductive oxide material electrically connected to the conductor. The conductive oxide materials is substantially amorphous, and the conductive oxide material includes first and second oxide materials. In addition, the first oxide material is different from the second oxide material. The electronic device also includes a second material, electrically connected to the conductive oxide material.Type: GrantFiled: August 20, 2019Date of Patent: September 28, 2021Assignee: 4DS MEMORY, LIMITEDInventor: Seshubabu Desu
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Patent number: 11127826Abstract: A semiconductor device may include a semiconductor substrate, an upper electrode provided on an upper surface of the semiconductor substrate, a lower electrode provided on a lower surface of the semiconductor substrate, and a terminal connected to the upper electrode. The semiconductor substrate may include an active region in which switching elements are provided. The switching elements may be configured to pass a current between the upper electrode and the lower electrode. The active region may include a main region located under the terminal and an external region located outside the main region. The external region may include a low current region. A current density in the low current region may be lower than a current density in the main region in a case where the switching elements in the low current region and the main region are turned on.Type: GrantFiled: June 24, 2020Date of Patent: September 21, 2021Assignee: DENSO CORPORATIONInventors: Masayuki Kamiya, Takanori Kawashima
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Patent number: 11121249Abstract: A semiconductor device of an embodiment includes a silicon carbide layer having a first plane and a second plane and includes a trench located on a first plane side and has a first region and a second region, a first silicon carbide region of an n-type, a second silicon carbide region of a p-type between the first silicon carbide region and the first plane, a third silicon carbide region of the n-type between the second silicon carbide region and the first plane, and a fourth silicon carbide region of the p-type between the second region and the first silicon carbide region; a gate electrode in the first region; a first electrode on the first plane side of the silicon carbide layer, a part of the first electrode is located in the second region and is in contact with the third and the fourth silicon carbide region; and a second electrode.Type: GrantFiled: February 24, 2020Date of Patent: September 14, 2021Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Shinya Kyogoku, Katsuhisa Tanaka, Ryosuke Iijima
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Patent number: 11114560Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate, a first semiconductor layer and a first semiconductor region each of a first conductivity type, and a first base region, a second semiconductor layer and a second semiconductor region each of a second conductivity type. The first base region opposes the second semiconductor region in a depth direction. A distribution of point defects in a depth direction from a first surface of the second semiconductor region, opposite a second surface of the second semiconductor region facing toward a front surface of the silicon carbide semiconductor substrate has two peaks at positions deeper than an interface between the first semiconductor layer and the first base region, where a first peak at a deeper position of the two peaks has a greater quantity of the point defects than does a second peak at a shallower position of the two peaks.Type: GrantFiled: March 2, 2020Date of Patent: September 7, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Keiji Okumura
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Patent number: 11107944Abstract: A method of manufacturing an optoelectronic semiconductor chip includes a) providing a semiconductor layer sequence having an active region that generates or receives radiation on a substrate; b) forming at least one recess extending through the active region; c) forming a metallic reinforcement layer on the semiconductor layer sequence by galvanic deposition, the metallic reinforcement layer completely covering the semiconductor layer sequence and at least partially filling the recess; and d) removing the substrate, wherein the metallic reinforcement layer is leveled on a side facing away from the semiconductor layer sequence.Type: GrantFiled: March 21, 2018Date of Patent: August 31, 2021Assignee: OSRAM OTPO GmbHInventors: Isabel Otto, Christian Leirer
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Patent number: 11107950Abstract: A light emitting chip includes a first-type semiconductor layer, a light emitting layer, and a second-type semiconductor layer which are disposed in such order, a passivation layer, and a current spreading layer. The second-type semiconductor layer and the light emitting layer cooperate to form a mesa structure which partially exposes the first-type semiconductor layer. The mesa structure has a lateral surface over which the passivation layer is disposed. The current spreading layer is disposed in contact with the second-type semiconductor layer. A distance between peripheries of a contact surface of the current spreading layer and a top surface of the second-type semiconductor layer is not greater than 5 ?m. A method for producing the chip is also disclosed.Type: GrantFiled: January 20, 2020Date of Patent: August 31, 2021Assignee: Xiamen San'an Optoelectronics Co., Ltd.Inventors: Yu-Tsai Teng, Yan Feng, Shuo Yang, Chung-Ying Chang, Shutian Qiu
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Patent number: 11107961Abstract: The ultraviolet light-emitting device includes a base, a nitride semiconductor ultraviolet light-emitting element flip-chip mounted on the base, and a lens for sealing a nitride semiconductor ultraviolet light-emitting element to focus or diffuse light emitted from the nitride semiconductor ultraviolet light-emitting device. The lens is composed of an amorphous fluororesin in which a structural unit of a polymer or copolymer has a fluorine-containing aliphatic cyclic structure and a terminal functional group is a perfluoroalkyl group, and a density of the amorphous fluororesin is higher than 2.11 g/cm3.Type: GrantFiled: November 2, 2017Date of Patent: August 31, 2021Assignees: SOKO KAGAKU CO., LTD., AGC INC.Inventors: Akira Hirano, Yosuke Nagasawa, Masamichi Ippommatsu, Ko Aosaki, Yuki Suehara, Yoshihiko Sakane
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Patent number: 11092864Abstract: A display panel and a display device are provided. The display panel includes a substrate; a first metal layer disposed on the substrate; an insulating layer disposed on the first metal layer; a semiconductor layer disposed on the insulating layer and including a germanium-doped semiconductor compound; and a second metal layer disposed on the semiconductor layer. A mobility of the semiconductor compound is greater than a mobility of amorphous silicon.Type: GrantFiled: May 22, 2017Date of Patent: August 17, 2021Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: En-Tsung Cho, Yiqun Tian
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Patent number: 11088184Abstract: An array substrate and a method of manufacturing the same are provided. The method of manufacturing an array substrate includes: forming a black matrix and an organic insulating pattern on a base substrate with a thin film transistor formed thereon, wherein the black matrix and the organic material pattern are formed by using an identical mask.Type: GrantFiled: September 15, 2017Date of Patent: August 10, 2021Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Na Zhao, Xufei Xu, Ru Zhou, Yue Shi
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Patent number: 11088176Abstract: The present disclosure provides a display device including an array substrate. At least one wiring on array is arranged on a surface of the array substrate, the wiring on array including a plurality of signal wires, and all the signal wires of the wiring on array being the same in impedance and different in length and in cross-sectional area. At least one first driving component is arranged at one side of the array substrate, adjacent first driving components being electrically connected via one wiring on array. At least one second driving component is arranged at the same side or different sides of the array substrate as the first driving member, adjacent second driving components being electrically connected via one wiring on array or adjacent first and second driving components being electrically connected via one wiring on array.Type: GrantFiled: September 7, 2018Date of Patent: August 10, 2021Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventor: Mancheng Zhou
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Patent number: 11075267Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects.Type: GrantFiled: December 16, 2019Date of Patent: July 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kuo-Yu Chou, Seiji Takahashi, Shang-Fu Yeh, Chih-Lin Lee, Chin Yin, Calvin Yi-Ping Chao
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Patent number: 11075081Abstract: A method for fabricating a semiconductor device with multiple threshold voltages includes masking a substrate structure to selectively form work-function metal layers on vertical field effect transistors. In the method, a first work function metal layer is formed on a high-k dielectric layer of a substrate structure comprising vertical field effect transistors. The first work function metal layer and the high-k dielectric layer are etched to form gate regions for each vertical field effect transistor. A resist mask is formed over a first of the vertical field effect transistors. The resist mask isolates the first of the vertical field effect transistors from a second of the vertical field effect transistors. A second work function metal layer is selectively formed on the first work function metal layer of the gate region of the second of the vertical field effect transistors. The resist mask is then removed.Type: GrantFiled: October 21, 2019Date of Patent: July 27, 2021Assignee: International Business Machines CorporationInventors: Praveen Joseph, Indira Seshadri, Ekmini Anuja De Silva