Patents Examined by J. H. Hur
  • Patent number: 11315646
    Abstract: A memory device includes: a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate string selection lines based on control of the control logic circuit. A program interval is formed between a first program operation and a second program operation. The control logic circuit includes a reprogram controller configured to control the row decoder so that a program interval differs in the memory cells connected to different string selection lines among the memory cells connected to a first wordline.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: April 26, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Bum Kim, Min-Su Kim, Deok-Woo Lee
  • Patent number: 11315621
    Abstract: A device includes an operation control circuit and a drive control signal generation circuit. The operation control circuit generates an internal refresh signal that is activated to perform an active operation for a cell array, the cell array being coupled to a word line that is selected by a row address based on a refresh signal that is activated to perform a refresh operation. In addition, the operation control circuit generates a pre-refresh pulse based on the refresh signal and generates a refresh end pulse based on the internal refresh signal. The drive control signal generation circuit generates a drive control signal to control a drive of an active voltage that is supplied to the word line that is selected by the row address based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: April 26, 2022
    Assignee: SK hynix Inc.
    Inventors: Kyung Mook Kim, Woongrae Kim, Sang Il Park, Seung Hun Lee
  • Patent number: 11309048
    Abstract: A method of testing using a memory test apparatus connected to a memory device includes receiving a test command. When the test command is a finite state machine (FSM) operation command, the memory device is tested in accordance with the FSM operation command, and an operation is performed to output a result depending on a pass/fail result. But, when the test command is a direct access command, an auto-operation test of input data is performed in a test region according to received address information, and a test result is output, which may include output data with fail information or the auto-operation.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: April 19, 2022
    Inventors: Hong-Mook Choi, Hye Soo Lee, Ji-Su Kang, Hyun Il Kim
  • Patent number: 11309057
    Abstract: Apparatuses and methods for post-package repair (PPR) protection. A device may enter a PPR mode to repair one or more memory addresses by blowing fuses. However, fuses may be incorrectly blown if the device receives row activation (ACT) signals while in the PPR mode. A PPR mask circuit may provide a PPR mask signal if an ACT signal is received while the memory is in the PPR mode. The PPR mask signal may suppress further ACT signals from being provided. In some embodiments, the memory may also include a PPR function circuit, which may monitor one or more signals used as part of PPR operations. If these signals are in an illegal state, the PPR function circuit may suppress PPR operations to prevent damage to the fuse array.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: April 19, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Takaaki Nakamura
  • Patent number: 11309006
    Abstract: A magnetic memory device includes a first magnetic structure having a magnetic anisotropy, a read electrode that is on an end of the first magnetic structure and configured to sense a first magnetic moment of the first magnetic structure and to convert the first magnetic moment to an electric signal, a second magnetic structure spaced apart from the first magnetic structure, the second magnetic structure having a magnetic anisotropy, and a write electrode that is on an end of the second magnetic structure and configured to change a second magnetic moment of the second magnetic structure, based on the electric signal. The magnetic memory device executes operations of writing, moving, and reading data on almost the entire region of the magnetic structure in a more efficient manner, compared with the conventional magnetic memory device.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: April 19, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Syuta Honda, Yoshiaki Sonobe
  • Patent number: 11295785
    Abstract: A memory system and storage device are provided, including: an auxiliary power device having at least one capacitor, wherein the at least one capacitor has a first path for leakage current; a charging circuit including a switch connected to the auxiliary power device; and a state determining circuit connected to the auxiliary power device, wherein the state determining circuit includes a path circuit connected in parallel with the at least one capacitor to form a second path having at least one of a resistance lower than a resistance of the first path or a current source.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woosung Lee, Chunghyun Ryu, Hyoungtaek Lim
  • Patent number: 11289158
    Abstract: An embodiment non-volatile memory device includes an array of memory cells, coupled to word lines, and a row decoder including a pull-down stage and a pull-up stage, which includes, for each word line: a corresponding control circuit, which generates a corresponding control signal; and a corresponding pull-up switch circuit, which is controlled via the control signal so as to couple/decouple the word line to/from the supply. The control circuit includes: a current mirror, which injects a current into an internal node; and a series circuit, which couples/decouples the corresponding internal node to/from ground, on the basis of selection/deselection of the corresponding word line so as to cause a decrease/increase in a voltage on the corresponding internal node. Each control signal is a function of the voltage on the corresponding internal node.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: March 29, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Fabio Enrico Carlo Disegni, Maurizio Francesco Perroni, Cesare Torti, Davide Manfré
  • Patent number: 11289142
    Abstract: The present invention is directed to a nonvolatile memory device including a plurality of memory slices, each memory slice including one or more memory sectors and a read circuit for sensing the resistance state of a magnetic memory cell in the memory sectors. The read circuit includes a first input node through which a reference current passes; a second input node through which a read current from the memory sectors passes; a sense amplifier configured to compare input voltages and having first and second input terminals; a reference resistor connected to the first input node at one end and the first input terminal at the other end; a variable current source connected to the reference resistor at one end and ground at the other end; and a second current source connected to the second input node at one end and ground at the other end.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: March 29, 2022
    Assignee: Avalanche Technology, Inc.
    Inventors: Thinh Tran, Ebrahim Abedifard
  • Patent number: 11289144
    Abstract: A non-volatile memory includes virtual ground circuitry configured to generate a virtual ground voltage at a virtual ground node, a memory array of memory cells in which each memory cell includes a select transistor and a storage element and is coupled to a first column line of a plurality of first column lines; and a first decoder configured to select a set of first column lines for a memory write operation to a selected set of the memory cells. The non-volatile memory also includes write circuitry configured to receive a write value for storage into the selected set of memory cells, and a first column line multiplexer configured to, during the memory write operation, couple each selected first column line of the set of first column lines to the write circuitry, and couple each unselected first column line of the plurality of first column lines to the virtual ground node.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: March 29, 2022
    Assignee: NXP USA, Inc.
    Inventors: Jon Scott Choy, Karthik Ramanan, Padmaraj Sanjeevarao, Jacob T. Williams
  • Patent number: 11276448
    Abstract: Methods, systems, and devices for memory array with multiplexed select lines are described. In some cases, a memory cell of the memory device may include a storage component, a first transistor coupled with a word line, and a second transistor coupled with a first select line to selectively couple the memory cell with a first digit line. A third transistor may be coupled with the first digit line and a sense component common to a set of digit lines and a set of select lines. A second select line may be coupled with the third transistor and configured to couple the sense component with the first digit line and to couple the sense component with a second digit line. The sense component may determine a logic state stored by the memory cell based on the signal from the first digit line and the signal from the second digit line.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 11232822
    Abstract: According to one embodiment, a magnetic memory includes a magnetic body with two portions of a first dimension in a first direction which are spaced from each other a second direction and another portion that has a second dimension less than the first dimension in the first direction, which is between the two other portions. A circuit supplies a shift pulse to the magnetic body. The shift pulse includes a first pulse and a second pulse and moves a domain wall in the magnetic body along the second direction. The first pulse has a first pulse width. The second pulse has a second pulse width less than the first pulse width. The second pulse is supplied to the magnetic body after the first pulse.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: January 25, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Michael Arnaud Quinsat, Tsuyoshi Kondo, Masahiro Koike, Shiho Nakamura, Susumu Hashimoto, Masaki Kado, Nobuyuki Umetsu, Yasuaki Ootera, Megumi Yakabe, Agung Setiadi, Shigeyuki Hirayama, Yoshihiro Ueda, Tsutomu Nakanishi
  • Patent number: 11233196
    Abstract: A memory device structure includes a substrate, a memory stacked structure, and a spacer. The memory stacked structure is formed on the substrate by stacking a first electrode layer, a memory material layer, and a second electrode layer. The memory material layer has a tilted sidewall, or the memory material layer and the first electrode layer have a tilted sidewall. The tilted sidewall is indented with respect to a sidewall of the second electrode layer. The spacer is disposed on the tilted sidewall.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: January 25, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Patent number: 11211107
    Abstract: The present invention is directed to a nonvolatile memory device that includes a plurality of memory slices, each memory slice including one or more memory sectors and a read circuit for sensing the resistance state of a magnetic memory cell in the memory sectors. The read circuit includes first and second input nodes; a sense amplifier having first and second input terminals; a first target resistor and a balancing resistor connected in series between the first input node and the first input terminal; a multiplexer having a first input, a second input, and an output, with the first input being connected to the second input node and the output being connected to the second input terminal; a second target resistor and an offset resistor connected in series between the second input node and the second input; and first and second current sources connected to the first and second input terminals, respectively.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: December 28, 2021
    Assignee: Avalanche Technology, Inc.
    Inventors: Thinh Tran, Ebrahim Abedifard
  • Patent number: 11205480
    Abstract: Methods and systems include memory devices with multiple access lines arranged in an array to form a multiple intersections. Memory cells are located at the intersections of the multiple access lines. Decoders are configured to drive the multiple memory cells via the multiple access lines. Variable biasing circuitry may bias a voltage on an access line of the multiple access lines to change a variable ramp rate of the voltage on the access line. A control circuit is configured to determine a memory cell of the multiple memory cells to be activated. Based at least in part on a distance from the memory cell to a corresponding decoder, the control circuit may set the variable ramp rate of the biasing circuitry.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Hari Giduturi
  • Patent number: 11205485
    Abstract: A memory device includes: a memory cell region; a peripheral circuit region; a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate string selection lines based on control of the control logic circuit. A program interval is formed between a first program operation and a second program operation. The control logic circuit includes a reprogram controller configured to control the row decoder so that a program interval differs in the memory cells connected to different string selection lines among the memory cells connected to a first wordline.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: December 21, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Bum Kim, Min-Su Kim, Deok-Woo Lee
  • Patent number: 11200929
    Abstract: Systems and methods for an optical ternary content addressable memory (TCAM) are provided. The optical TCAM implements a time-division multiplexing (TDM) based encoding scheme to encode each bit position of a search word in the time domain. Each bit position is associated with at least two time slots. The encoded optical signal comprising the search word is routed through one or more modulators configured to represent a respective TCAM stored word. If a mismatch between at least one bit position of the search word and at least one TCAM stored word occurs, a photodetector or photodetector array will detect light.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: December 14, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Thomas Van Vaerenbergh, Can Li, Catherine Graves
  • Patent number: 11189354
    Abstract: A nonvolatile memory device capable of minimizing monitoring overhead associated with read disturb is provided. The nonvolatile memory device includes a memory cell array which includes a first cell string comprising a plurality of memory cells connected in series, wherein the plurality of memory cells includes a first monitoring cell, a first memory cell, and a second memory cell, and a row decoder which provides a first read voltage to the first memory cell and a first monitoring voltage to the first monitoring cell when reading the first memory cell among the memory cells and provides the first read voltage to the second memory cell and a second monitoring voltage different from the first monitoring voltage to the first monitoring cell when reading the second memory cell.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: November 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Woo Lee, Chan Ha Kim, Hee Won Lee
  • Patent number: 11183228
    Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element; a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: November 23, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Hideo Ohno, Tetsuo Endoh
  • Patent number: 11182241
    Abstract: Methods, systems, and devices for spare substitution in a memory system are described. A controller may, as part of a background operation, assign a spare bit to replace a bit of a code word and save an indication of the spare bit assignment in a memory array. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) within a memory medium that retains the code word. An MSR corresponding to the bit to be replaced may include a quantity of erroneous bits relative to a threshold. The controller may, during a read operation, identify the spare bit in a first portion of the code word, determine the bit to be replaced based on accessing the memory array, and replace the bit with the spare bit concurrently with receiving a second portion of the code word.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Joseph T. Pawlowski
  • Patent number: 11164654
    Abstract: A method drives an electronic device including a semiconductor memory in a test mode. The method includes applying a stress pulse simultaneously to a plurality of memory cells to turn on the plurality of memory cells, determining whether the memory cells are turned on or turned off, and applying a second maximum voltage to a selected memory cell of the plurality of memory cells only when the selected memory cell is determined to be in a turned-off state.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: November 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Sang-Hyun Ban, Tae-Hoon Kim, Woo-Tae Lee, Hye-Jung Choi