Abstract: Methods, systems, and devices related to access schemes for access line faults in a memory device are described. In one example, a method may include isolating a first word line of a section of a memory device from a voltage source (e.g., a deselection voltage source) during a first portion of a period when the first word line is deselected, and coupling the first word line with the voltage source during a second portion of the period when the first word line is deselected based on determining that an access operation is performed during the second portion of the period when the word line is deselected. In some examples, the method may include identifying that the first word line is associated with a fault, such as a short circuit fault with a digit line of the memory device.

Abstract: A memory unit is controlled by a first word line and a second word line. The memory unit includes a memory cell and a multi-bit input local computing cell. The memory cell stores a weight. The memory cell is controlled by the first word line and includes a local bit line transmitting the weight. The multi-bit input local computing cell is connected to the memory cell and receives the weight via the local bit line. The multi-bit input local computing cell includes a plurality of input lines and a plurality of output lines. Each of the input lines transmits a multi-bit input value, and the multi-bit input local computing cell is controlled by the second word line to generate a multi-bit output value on each of the output lines according to the multi-bit input value multiplied by the weight.

Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

Abstract: A memory device includes a cell array including a memory cell that includes a variable resistance element, a reference resistor configured to provide a resistance varying according to an adjustment code, and a read circuit configured to read data that is stored in the memory cell, based on a resistance of the variable resistance element and the resistance of the reference resistor. The memory device further includes a reference adjustment circuit configured to obtain a first calibration code corresponding to a temperature variation, and a second calibration code corresponding to a process variation, and perform an arithmetic operation on the obtained first calibration code and the obtained second calibration code, to obtain the adjustment code.

Abstract: A magnetic memory device includes: a memory cell array including a plurality of lines arranged parallel to one another at predetermined intervals and extending in one direction, and a plurality of memory cells connected to the plurality of lines and arranged in a matrix along an extending direction of the plurality of lines and along an arrangement direction of the plurality of lines, each of the plurality of memory cells including a magnetoresistance effect element; a selection circuit connected to the plurality of lines and configured to select non-adjacent lines that are not adjacent to one another, from the plurality of lines; and a controller connected to the selection circuit and configured to cause the selection circuit to select the non-adjacent lines and allow a write current to flow through the non-adjacent lines simultaneously in writing data on the memory cell array.

Abstract: Counters may be provided for individual word lines of a memory for tracking word line accesses. In some examples, multiple counters may be provided for individual word lines. In some examples, the counters may be included on the word lines. The counters may be incremented responsive to word line accesses in some examples. In some examples, the counters may be incremented responsive for a time period for which a word line is held open. In some examples, the counters may be incremented responsive to both word line accesses and time periods for which the word line is held open. In some examples, count values for the counters may be written back to the counters after incrementing. In some examples, the count values may be written back prior to receiving a precharge command.

Abstract: A memory device includes a syndrome generating circuit and a plurality of latch circuits. The syndrome generating circuit includes a plurality of input terminals and plurality of logic circuits. The latch circuits are coupled to the syndrome generating circuit and are configured to set the input terminals of the syndrome generating circuit to a predetermined logic state according to a pre-charge reset signal. The latch circuits are configured to provide a plurality of data bits to the input terminals of the syndrome generating circuit after the input terminals of the syndrome generating circuit are set to the predetermined logic state. The syndrome generating circuit is configured to generate a syndrome bit based on the data bits by the logic circuits, wherein the syndrome bit indicates a presence of an error bit among the data bits.

Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.

Abstract: Memory devices and methods for operating the same are described. The memory devices may include non-volatile memory having a plurality of memory cells, and a controller. The controller may be configured to begin a first programming operation configured to program a first one of the plurality of memory cells with more than one bit of information, terminate the first programming operation in response to detecting a power loss event, and program, with a second programming operation, second and third ones of the plurality of memory cells with the more than one bit of information.

Abstract: A semiconductor storing apparatus capable of performing continuous readout between multiple chips in high speed is provided. A NAND-type flash memory includes the stacked multiple chips. Each of the chips includes: a readout part performing the continuous readout; an output buffer part outputting data readout from the readout part to input/output bus synchronously with a clock signal; and a final page detecting part detecting if readout pages are the final pages of the chips. The output buffer part responds to a detecting result of the final pages under a condition of performing the continuous readout between the chips. After outputting the data of the final pages through a first output buffer with a large driving capability, outputs or holds the data of the final pages through a second output buffer with a little driving capability.

Abstract: A memory device and its addressing method are disclosed. The memory device includes: an input module for receiving an input signal including an access address, a command, and a decoding selection instruction; a memory array including memory blocks, each having memory units arranged in an array; and a control module including memory block local control units, which respectively connected to one of the memory blocks in one-to-one correspondence. The memory block local control unit includes: at least one decoding unit, which performs redundant decoding or normal decoding to the input signal. The input of the decoding unit is coupled to the input module and the output is coupled to one of the memory units. The device further includes a selection module; the input of the selection module is coupled to the input module, and the output is coupled to the decoding unit. The addressing efficiency of the memory device is improved.

Abstract: Some embodiments include an integrated assembly having a base supporting first circuitry and first conductive lines. The first conductive lines extend along a first direction and are associated with the first circuitry. A deck is over the base and supports an array of memory cells and second conductive lines which are associated with the array of memory cells. The second conductive lines extend along a second direction which is substantially orthogonal to the first direction. Vertical interconnects extend from the deck to the base and couple the first conductive lines to the second conductive lines. Each of the vertical interconnects couples one of the first conductive lines to one of the second conductive lines. Each of the second conductive lines is coupled with only one of the first conductive lines.

Abstract: A memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer. A second portion of the second program line is formed in the second conductive layer. A third portion of the second program line is formed in a third conductive layer above the second conductive layer. The first portion and the second portion of the first program line have sizes that are different from each other, and the first portion, the second portion and the third portion of the second program line have sizes that are different from each other.

Abstract: A memory system includes a semiconductor storage device, a power supply circuit that generates a first power, and a memory controller that operates based on the first power and transmits a command to the semiconductor storage device. The semiconductor storage device includes a first terminal, a second terminal, a word line, a first circuit, and a second circuit. The first power is input to the first terminal. A second power that can be used even after a voltage of the first terminal decreases is input to the second terminal. The word line is connected to a control gate of a memory cell transistor. The first circuit applies a voltage according to the command to the word line based on the first power input to the first terminal. The second circuit discharges charges of the word line by using the second power input to the second terminal when a voltage of the first terminal decreases.

Abstract: The present disclosure includes apparatuses and methods related to comparing data patterns in memory. An example method can include comparing a number of data patterns stored in a memory array to a target data pattern. The method can include determining whether a data pattern of the number of data patterns matches the target data pattern without transferring data from the memory array via an input/output (I/O) line.

Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may turned on while the pMOSFET is turned off. The nMOSFET provides a higher resistance in place of the decreased resistance of the pMOSFET to amplify a signal at a sense circuit to allow accurate sensing of the voltage across the memory cell.

Abstract: A resistive memory device includes a first bit line group including a first edge bit line, a second bit line group including a second edge bit line, and a first boundary transistor configured to apply a non-selection voltage to the second edge bit line according to a selection of the first edge bit line. The first edge bit line of the first bit line group is disposed closest to the second bit line group, and the second edge bit line of the second bit line group is disposed closest to the first bit line group.

Abstract: A memory device may include: a control circuit comprising a first verification component suitable for counting the number of memory cells in the selected word line having an excessively high threshold voltage as excessive memory cells, after a program operation is completed; and a second verification component suitable for counting the number of failed bits when the number of excessive memory cells counted is greater than or equal to an excess threshold value, and suitable for outputting a pass or fail signal for the program operation according to the count of at least one of the first verification component and the second verification component.

Abstract: The disclosed system and method reduce on-chip power IR drop caused by large write current, to increase the write IO number or improve write throughput and to suppress write voltage ripple at the start and end of a write operation. The disclosed systems and methods are described in relation to stabilizing the bit line voltage for MRAMs, however, the disclosed systems and methods can be used to stabilize the bit line voltage of any memory configuration that draws large currents during short write pulses or, more generally, to selectively assist a power supply generator in supplying adequate power to a load at times of large power consumption.

Abstract: A memory includes virtual ground circuitry configured to generate a virtual ground voltage (greater than zero volts) at a virtual ground node, a memory array of resistive memory cells in which each resistive memory cell includes a select transistor and a resistive storage element and is coupled to a first column line of a plurality of first column lines, and a first decoder configured to select a set of first column lines for a memory read operation from a selected set of the resistive memory cells. The memory includes read circuitry, and a first column line multiplexer configured to couple each selected first column line of the set of first column lines to the read circuitry during the memory read operation, and configured to couple each unselected first column line of the plurality of first column lines to the virtual ground node during the memory read operation.