Patents Examined by J. H. Hur
  • Safe destructive actions on drives
    Patent number: 10929053
    Abstract: A method for reservations in a storage system, is provided. The method includes determining status of all storage devices expected to be in the storage system, receiving a request for a reservation of a storage device, and determining a type of service to be performed on the storage device. The method includes determining whether the type of service is in a first class of services or a second class of services and granting or denying the reservation based on the type of service, wherein a reservation to perform a service in the first class of services is granted as a result of determining all the storage devices expected are online and wherein a reservation to perform a service in the second class of services is granted as a result of determining a sufficient subset of all the storage devices expected are online to perform reading and writing with redundancy.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: February 23, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Andrew R. Bernat, Pushkar Mahesh Shirali, Anthony Niven
  • Location dependent impedance mitigation in non-volatile memory
    Patent number: 10910064
    Abstract: An apparatus comprising strings of non-volatile memory cells, a first set of pathways connected to the strings, and a second set of pathways connected to the strings. The first set of pathways have first impedances that depend on location of respective strings. The second set of pathways having second impedances. The apparatus also includes one or more control circuits configured to compensate for location dependent impedance mismatch between the first set of pathways and the second set of pathways during memory operations on the non-volatile memory cells.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: February 2, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Peter Rabkin, Kwang-Ho Kim, Masaaki Higashitani
  • Magnetoresistive memory device with different write pulse patterns
    Patent number: 10910032
    Abstract: A memory device includes a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers. The memory device also includes a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a write current to the magnetoresistive element. A first write current in the first writing includes a first pulse and a second pulse added to the first pulse. A width of the second pulse is smaller than a width of the first pulse, and a current level of the second pulse is different from a current level of the first pulse.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: February 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuya Kishi, Tsuneo Inaba, Daisuke Watanabe, Masahiko Nakayama, Nobuyuki Ogata, Masaru Toko, Hisanori Aikawa, Jyunichi Ozeki, Toshihiko Nagase, Young Min Eeh, Kazuya Sawada
  • Access schemes for access line faults in a memory device
    Patent number: 10902935
    Abstract: Methods, systems, and devices related to access schemes for access line faults in a memory device are described. In one example, a method may include isolating a first word line of a section of a memory device from a voltage source (e.g., a deselection voltage source) during a first portion of a period when the first word line is deselected, and coupling the first word line with the voltage source during a second portion of the period when the first word line is deselected based on determining that an access operation is performed during the second portion of the period when the word line is deselected. In some examples, the method may include identifying that the first word line is associated with a fault, such as a short circuit fault with a digit line of the memory device.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yasushi Matsubara
  • Ferroelectric memory-based synapses
    Patent number: 10885963
    Abstract: An embodiment includes an apparatus comprising: a first layer and a second layer; a first gate including first gate portions and a second gate including second gate portions; wherein the first layer: (a) is monolithic, (b) is between the first gate portions and is also between the second gate portions, and (c) includes a semiconductor material; wherein the second layer: (a) is between the first layer and at least one of the first gate portions and is also between the first layer and at least one of the second gate portions, and (b) includes oxygen and at least one of hafnium, silicon, yttrium, zirconium, barium, titanium, lead, or combinations thereof; wherein (a) a first plane intersects the first gate portions and the first and second layers, and (b) a second plane intersects the second gate portions and the first and second layers. Other embodiments are described herein.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Dmitri Nikonov, Ilya Karpov, Ian Young
  • Dynamic random access memory array, semiconductor layout structure and fabrication method thereof
    Patent number: 10885956
    Abstract: A semiconductor layout structure for a dynamic random access memory (DRAM) array, comprising an isolation structure and a plurality of active areas situated in a semiconductor substrate, each of the active areas extending along a length-wise central axis. The isolation structure is situated among the active areas. The active areas are arranged in an array and comprise a plurality of first active areas and a plurality of second active areas. The first active areas are arranged along a first length-wise direction of the active areas. The second active areas are arranged along a second length-wise direction of the active areas. The first active areas are parallel and adjacent to the second active areas, and the first and second active areas are alternately distributed in a direction of word-lines. The first active area having a first width smaller than a second width of the second active area.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: January 5, 2021
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chih Cheng Liu
  • Reading even data lines or odd data lines coupled to memory cell strings
    Patent number: 10885987
    Abstract: A method for reading an array of memory cells includes enabling a current to flow through even data lines of the array of memory cells. The method includes blocking a current from flowing through odd data lines of the array of memory cells. The method includes sensing data stored in memory cells coupled to the even data lines.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Andrea D'Alessandro, Tommaso Vali, Giovanni Santin
  • Data storage management in a device including removable and embedded storage areas
    Patent number: 10872663
    Abstract: A device includes a first signal line, a second signal line, and a controller. The first signal line is coupled to a first storage area. The second signal line is coupled to a second storage area. The controller outputs a signal to the first signal line or the second signal line to select the first storage area or the second storage area. The first storage area may be a removable data storage card, and the second storage area may be an embedded storage area in the device. The signal is a reset signal for the selected one of the first storage area and the second storage area.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: December 22, 2020
    Assignee: NXP B.V.
    Inventors: Fabien Boitard, Ludovic Oddoart
  • Semiconductor memory device for resetting counter synchronized with data clock by using reset signal synchronized with system clock and method for operating the same
    Patent number: 10861515
    Abstract: An operating method for a semiconductor memory device includes: generating a whole-domain-crossing-unit reset signal based on a domain-crossing-unit reset signal input to a whole-domain-crossing-unit-reset-signal generator; and resetting a counter synchronized to a data clock of a domain-crossing unit based on the whole-domain-crossing-unit reset signal during a data clock preparation section in which the data clock does not toggle.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventors: Kang-Sub Kwak, Sang-Sic Yoon, Young-Jun Yoon
  • Clocked commands timing adjustments method in synchronous semiconductor integrated circuits
    Patent number: 10832747
    Abstract: A method in a clocked integrated circuit receiving an input clock signal having a clock frequency and a command signal for accessing a memory element in the clocked integrated circuit. The method detects the input clock signal having a clock frequency above or below a frequency threshold. The method generates a clock detect output signal having a first logical state in response to the clock frequency being below the frequency threshold and generates the clock detect output signal having a second logical state in response to the clock frequency being above the frequency threshold. The method delays the command signal by a first timing latency to generate a timing adjusted control signal where the first timing latency is one or more clock periods of the input clock signal. Finally, the method adjusts the first timing latency in response to the clock detect output signal.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: November 10, 2020
    Assignee: Integrated Silicon Solution, Inc.
    Inventors: Steven Eaton, Matthew Manning
  • Global bit line latch performance and power optimization
    Patent number: 10832763
    Abstract: Embodiments for global bit line latch performance and power optimization are described herein. An aspect includes a bit line including a first section, a second section, and coupling circuitry arranged between the first section and the second section, the coupling circuitry adapted to causes a voltage drop between the first section and the second section, and at least one logic element including a first branch connected to a first power supply and a second branch connected to a second power supply, wherein the first branch is connected to the first section of the bit line, and wherein the second branch is connected to the second section of the bit line.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin Bernhard Schmidt, Harry Barowski, Alexander Fritsch, Matthias Hock
  • Integrated assemblies comprising vertically-stacked decks of memory arrays
    Patent number: 10833059
    Abstract: Some embodiments include an integrated assembly having a base supporting first circuitry and first conductive lines. The first conductive lines extend along a first direction and are associated with the first circuitry. A deck is over the base and supports an array of memory cells and second conductive lines which are associated with the array of memory cells. The second conductive lines extend along a second direction which is substantially orthogonal to the first direction. Vertical interconnects extend from the deck to the base and couple the first conductive lines to the second conductive lines. Each of the vertical interconnects couples one of the first conductive lines to one of the second conductive lines. Each of the second conductive lines is coupled with only one of the first conductive lines.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Memory device with a common source select line for two memory portions of a logic sector
    Patent number: 10825524
    Abstract: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Luigi Pascucci, Paolo Rolandi
  • Programming non-volatile electronic memory device with NAND architecture
    Patent number: 10825525
    Abstract: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Luigi Pascucci, Paolo Rolandi
  • Test modes for a semiconductor memory device with stacked memory chips using a chip identification
    Patent number: 10818372
    Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device controls a test mode. The first semiconductor device outputs a chip identification and receives external data. The second semiconductor device includes a plurality of memory chips. At least one of the plurality of memory chips are activated based on the chip identification to store input data into each of the plurality of memory chips that have been activated while a write operation is performed in the test mode. At least two of the plurality of memory chips are activated based on the chip identification to output the stored input data as the external data while a read operation is performed in the test mode.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: October 27, 2020
    Assignee: SK hynix Inc.
    Inventor: Seong Ju Lee
  • Multi-pass programming process for memory device which omits verify test in first program pass
    Patent number: 10811109
    Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: October 20, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Ashish Baraskar, Ching-Huang Lu, Vinh Diep, Yingda Dong
  • Access assist with wordline adjustment with tracking cell
    Patent number: 10811088
    Abstract: Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 20, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Pradeep Raj, Rahul Sahu, Sharad Kumar Gupta
  • Semiconductor memory capable of reducing an initial turn-on voltage of a memory cell using a stress pulse in a test mode, and method for driving the same
    Patent number: 10783981
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first lines; a plurality of second lines; a plurality of memory cells disposed in respective intersection regions between the first lines and the second lines and coupled between the first lines and the second lines, the plurality of memory cells having a first turn-on voltage; and a test circuit block suitable for applying a stress pulse having a voltage level equal to or higher than the first turn-on voltage to one or more first lines selected from the first lines in a test mode.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: September 22, 2020
    Assignee: SK hynix Inc.
    Inventors: Sang-Hyun Ban, Tae-Hoon Kim, Woo-Tae Lee, Hye-Jung Choi
  • Verification of an excessively high threshold voltage in a memory device
    Patent number: 10783974
    Abstract: A memory device may include: a control circuit comprising a first verification component suitable for counting the number of memory cells in the selected word line having an excessively high threshold voltage as excessive memory cells, after a program operation is completed; and a second verification component suitable for counting the number of failed bits when the number of excessive memory cells counted is greater than or equal to an excess threshold value, and suitable for outputting a pass or fail signal for the program operation according to the count of at least one of the first verification component and the second verification component.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 22, 2020
    Assignee: SK hynix Inc.
    Inventor: Sang-Sik Kim
  • Cross-point storage array including correlated electron switches
    Patent number: 10777273
    Abstract: A device comprising a storage array, the storage array comprising a first signal line and a second signal line, at least one correlated electron switch in electrical communication with the first signal line and the second signal line, and control circuitry for driving the correlated electron switch with at least one programming signal.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: September 15, 2020
    Assignee: Arm LTD
    Inventors: Shidhartha Das, James Edward Myers, Seng Oon Toh