Patents Examined by J. L. Badgett
  • Patent number: 4473833
    Abstract: An asymmetrical interferometer having two Josephson junctions with unequal contact areas. In accordance with the invention, the magnetic flux magnitudes of the control lines of the Josephson junctions are approximately equal in each Josephson junction. In a preferred embodiment, the length of the Josephson junctions along a direction parallel to the control line are equal to each other. Moreover, each Josephson junction is provided with a counterelectrode metalization, the counterelectrode metalizations having substantially equal widths measured in a direction orthogonal to the control line. The widths of the counterelectrode metalizations are larger than the width of an inductive connection between the Josephson junctions.
    Type: Grant
    Filed: March 3, 1981
    Date of Patent: September 25, 1984
    Assignee: Universitat Karlsruhe
    Inventors: Hansjorg Beha, Wilhelm Jutzi
  • Patent number: 4471376
    Abstract: An amorphous semiconductor device on a silicon substrate having a first level contact and interconnect of aluminum and coextensive layer of molybdenum and a second level contact and interconnect of molybdenum and coextensive layer of aluminum. Contacts to the amorphous device are by the two molybdenum layers and the contact of the second level contacts to the substrate is through the first level contacts.
    Type: Grant
    Filed: January 14, 1981
    Date of Patent: September 11, 1984
    Assignee: Harris Corporation
    Inventors: William R. Morcom, Glenn M. Friedman
  • Patent number: 4468686
    Abstract: An improved field terminating structure for a semiconductor device provides a well defined voltage gradient in the vicinity of a p-n junction to reduce the electric field near the junction and increase the junction breakdown voltage. The structure includes one or more MOS-type field effect transistors operably connected to one of the regions of the junction. A portion of the potential difference applied across the junction corresponding to the threshold voltage of each transistor is distributed across the surface of the device near the junction.
    Type: Grant
    Filed: November 13, 1981
    Date of Patent: August 28, 1984
    Assignee: Intersil, Inc.
    Inventor: Bruce Rosenthal
  • Patent number: 4468719
    Abstract: A porous body of Ti-Al alloy has a novel structure for a solid electrolytic capacitor, having improved values of leakage current and dielectric loss. The porous body of Ti-Al alloy has spherical particles which partially contact each other to form an integral body. The surfaces of the spherical particles have a ruggedness in the order of several microns or less. Because the diameter of the spherical particle is greater than the size of the ruggedness, the porous body has rough voids which provide a wide passageway through which a manganese nitrate solution penetrates. The wide passageway is effective for decreasing the number of times when there is a thermal decomposition of the manganese nitrate, thereby reducing the series resistance of the resultant cathode. In addition, this novel structure makes it possible to avoid production difficulties which are usually encountered when a solid electrolytic capacitor, having a high capacitance, is produced from a finely divided Ti-Al alloy.
    Type: Grant
    Filed: April 2, 1981
    Date of Patent: August 28, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Shigeaki Shimizu, Yoshimi Kubo, Tetsuo Suzuki, Takashi Kizaki, Hitoshi Igarashi
  • Patent number: 4464673
    Abstract: A semiconductor component, which may be configured as a diac or triac or the like, has a semiconductor body comprising four layers of alternating conductivity type, in which an outer n-emitter carries a cathode, an outer p-emitter carries an anode, and two base layers are respectively adjacent and between the emitter layers. The anode and cathode respectively have terminals for an external circuit and a metal-insulator-semiconductor structure is disposed adjacent the n-emitter layer (p-emitter layer), the metal-insulator-semiconductor structure being provided with a gate electrode insulated from the boundary surface of the semiconductor body and representing a controllable emitter short circuit. A resistor is connected to the cathode (anode) and is connected in an external circuit in series with the cathode terminal (anode terminal).
    Type: Grant
    Filed: April 9, 1981
    Date of Patent: August 7, 1984
    Assignee: Siemens Aktiengesellschaft
    Inventor: Hubert Patalong
  • Patent number: 4454526
    Abstract: A semiconductor image sensor of wide dynamic range, high sensitivity, low noise and high image clarity, which is provided with a hook structure for detecting radiant energy input information, a readout transistor and means for refreshing stored optical information and which is capable of non-destructive readout of optical information, and a method of operating such a semiconductor image sensor. The impurity concentrations in the hook structure, their distribution profiles, materials of layers forming the hook structure and their thicknesses are so selected as to optimize the carrier storage function of the hook structure, thereby permitting the non-destructive readout of the optical information. The ratio between the junction capacitance and the earth capacitance of a floating pn junction establishing a potential barrier in the hook structure is selected so that a stored voltage in the floating pn junction and the readout sensitivity may become maximum.
    Type: Grant
    Filed: May 20, 1981
    Date of Patent: June 12, 1984
    Assignee: Semiconductor Research Foundation
    Inventors: Jun-ichi Nishizawa, Tadahiro Ohmi, Takashige Tamamushi
  • Patent number: 4454527
    Abstract: A thyristor which has outer emitter layers of opposite conductivity types and intermediate base layers of respective opposite conductivity types and metal-insulated-semiconductor emitter short circuit structures including a semiconductor region inserted in one of the outer emitters and doped opposite thereto and connected to the electrode carried thereby has an electrically conductive coating, connected to a terminal, carried on the boundary surface of the semiconductor body which contains the emitter layer having the MIS structure, a lateral zone of the conductive coating being insulated from the boundary surface and forming a gate electrode of the MIS structure and another zone which contacts the boundary surface and forms the trigger electrode.
    Type: Grant
    Filed: April 9, 1981
    Date of Patent: June 12, 1984
    Assignee: Siemens Aktiengesellschaft
    Inventor: Hubert Patalong
  • Patent number: 4454523
    Abstract: A high voltage field effect transistor includes a source region in a first major surface of a semiconductor body and a drain region in a second major surface of the semiconductor body. A first gate region is formed in the first major surface and is surrounded by the source regions. A second gate region surrounds the source region and includes a buried region extending into the semiconductor body between the source and drain regions. The buried gate structure can be fabricated by epitaxial grown over diffused regions in a semiconductor substrate, or alternatively ion implantation can be employed to form the buried gate regions.
    Type: Grant
    Filed: March 30, 1981
    Date of Patent: June 12, 1984
    Assignee: Siliconix Incorporated
    Inventor: Lorimer K. Hill
  • Patent number: 4454529
    Abstract: The present invention is directed to an integrated circuit device comprising a lead frame having a ceramic capacitor mounted thereon and forming the support for a silicon chip bearing a multiplicity of circuits, including at least two power supply circuits namely a main power supply circuit and a secondary circuit. The capacitor is shunted across the terminals of the main power supply and the main power terminals of said IC chip. A conductive layer disposed atop the ceramic uppermost layer of the capacitor defines with the uppermost electrode of the capacitor, a second capacitive load of lesser value than the main capacitor, the said second capacitive load being shunted across the terminals of the secondary power supply and a secondary set of power terminals of said chip.
    Type: Grant
    Filed: January 15, 1982
    Date of Patent: June 12, 1984
    Assignee: AVX Corporation
    Inventors: Elliott Philofsky, Ward Parkinson, Dennis Wilson
  • Patent number: 4451845
    Abstract: The present invention is directed to an IC device of the ceramic encapsulated type wherein a power supply pulse dampening capacitor is embodied within the IC housing. The device is characterized by the utilization of a chip capacitor bonded to the floor of a recess formed within the housing, which capacitor forms a platform supporting the IC device. Leads between the capacitor and the power supply terminals of the circuit may be maintained at extremely short lengths, whereby inductances are minimized and relatively small capacitors effectively damp power supply pulses.
    Type: Grant
    Filed: December 22, 1981
    Date of Patent: May 29, 1984
    Assignee: AVX Corporation
    Inventors: Elliott Philofsky, Ward Parkinson, Dennis Wilson
  • Patent number: 4450461
    Abstract: A high isolation voltage optocoupler includes spaced apart emitter and detector elements coupled to one and the other ends of a bar of light transmissive dielectric material. A reflective coating on the surface of the bar enhances light coupling. An opaque dielectric housing excludes ambient light and provides mechanical support for the coupling elements.
    Type: Grant
    Filed: July 24, 1981
    Date of Patent: May 22, 1984
    Assignee: General Electric Company
    Inventors: James S. Cook, J. Anthony Lennon
  • Patent number: 4450466
    Abstract: A semiconductor image sensor which comprises a plurality of image sensor cells, each having a photosensing and accumulation region of an n.sup.+ -p.sup.- -(i)-p.sup.+ -n.sup.+ (or p.sup.+ -n.sup.- -(i)-n.sup.+ -p.sup.+) hook structure which is formed by sequentially forming its respective regions in a semiconductor substrate inwardly thereof from its surface. The photosensing and accumulation regions are isolated by insulating isolation regions from adjacent ones of them. A tapering conductive region, which acts as an electric field lens on charged carriers, is formed to extend into a high resistivity layer of the photosensing region from the end face of each insulating isolation region on the side of the semiconductor substrate.
    Type: Grant
    Filed: December 2, 1981
    Date of Patent: May 22, 1984
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Jun-ichi Nishizawa, Tadahiro Ohmi, Seiji Matsumoto
  • Patent number: 4449140
    Abstract: Two and three terminal semi-conductor barrier switching devices are disclosed in which a semi-conductor junction or a Schottky barrier is used to inject carriers towards a barrier formed by a narrow layer doped to have majority carriers of the type injected. In the non-conducting state the barrier prevents conduction but as an applied bias is increased the barrier begins to allow carriers of the opposite type to pass releasing the first mentioned carriers and causing the barrier height to be reduced. This action becomes regenerative with increasing bias and after passing through a negative resistance region, the device enters its conducting state. When the third terminal is present the device is made conducting by biasing its third terminal to cause carriers of the first mentioned type to be injected into the barrier region for example from a diffusion adjacent to the third terminal.
    Type: Grant
    Filed: December 24, 1981
    Date of Patent: May 15, 1984
    Assignee: National Research Development Corporation
    Inventor: Kenneth Board
  • Patent number: 4446477
    Abstract: A novel thin film processing substrate is embodied into a multichip hybrid module. The processing substrate is provided with conductive vias which are arranged in an area array having the same pattern as the lead out pin vias on a base substrate. The top surface of the processing substrate is built up by thin film techniques to provide a laminate thereon comprising a ground plane and a plurality of thin film X-direction and Y-direction signal distribution lines separated one from the other by thin polyimide insulating layers. The interconnecting thin film lines and polyimide layers are built up as patterns using photolithographic techniques. The X and Y-direction conductive lines and the ground plane are selectively interconnected through the vias and each other to form a predetermined signal distribution circuit.
    Type: Grant
    Filed: August 21, 1981
    Date of Patent: May 1, 1984
    Assignee: Sperry Corporation
    Inventors: Thomas P. Currie, Norman Goldberg
  • Patent number: 4443808
    Abstract: A semiconductor device having a high breakdown voltage transistor and a Schottky barrier diode. The Schottky barrier diode is formed in a surface portion of a semiconductor layer adjacent to the base region of the transistor, and a well layer of the same conductivity type as and of a lower impurity concentration that of the aforementioned semiconductor layer is formed under the Schottky barrier diode.
    Type: Grant
    Filed: April 2, 1982
    Date of Patent: April 17, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kazuo Kihara, Masashi Ikeda
  • Patent number: 4441119
    Abstract: An improved integrated circuit package (10) includes a cover (12), an intermediate subassembly (14) and a bottom subassembly (16). The intermediate and bottom subassemblies (14, 16) include lead frames (48, 22) respectively embedded therein, as well as openings which define a cavity for a semiconductor chip. The external lead pins (24) of the bottom subassembly (16) permit interconnection of the package with a circuit board or the like, while the external contacts (50) of the intermediate subassembly (14) cooperate with openings (62) in the cover to provide integral socket connections for other semiconductor packages or electrical components.
    Type: Grant
    Filed: January 15, 1981
    Date of Patent: April 3, 1984
    Assignee: Mostek Corporation
    Inventor: Joseph Link
  • Patent number: 4441113
    Abstract: The production of improved photoresponsive amorphous alloys and devices, such as photovoltaic, photoreceptive devices and the like; having improved wavelength threshold characteristics is made possible by adding one or more band gap increasing elements to the alloys and devices. The increasing element or elements are added at least to a portion of the active photoresponsive regions of amorphous silicon devices. One increasing element is carbon which increases the band gap from that of the materials without the increasing element incorporated therein. Other increasing elements can be used such as nitrogen. The silicon and increasing elements are concurrently combined and deposited as amorphous alloys by vapor deposition, sputtering or glow discharge decomposition. A density of states reducing element allows the band gap increasing element(s) to be added to the alloy to adjust the band gap without reducing the electronic qualities of the alloy.
    Type: Grant
    Filed: February 13, 1981
    Date of Patent: April 3, 1984
    Assignee: Energy Conversion Devices, Inc.
    Inventor: Arun Madan
  • Patent number: 4438445
    Abstract: A variable capacitance diode comprises a low resistance semi-conductor substrate on which is epitaxially deposited three layers, a first layer adjacent the substrate having an impurity concentration which decreases towards the substrate, a very thin intermediate region and a relatively thin surface region of lower doping than the intermediate region, a barrier being formed on or in the outer surface of the relativey thin surface region.The invention also includes a method of making such a diode.
    Type: Grant
    Filed: July 8, 1981
    Date of Patent: March 20, 1984
    Assignee: Telefunken Electronic GmbH
    Inventors: Alexander Colquhoun, Erhard Kohn
  • Patent number: 4437108
    Abstract: A contact structure in a double polysilicon device is described in which direct shorts between overlying polysilicon conductors due to a "polysilicon void phenomenon" is overcome by patterning an appropriate etch stop between the conductors.
    Type: Grant
    Filed: December 20, 1982
    Date of Patent: March 13, 1984
    Assignee: International Business Machines Corporation
    Inventors: James R. Gardiner, Stanley R. Makarewicz, Martin Revitz, Joseph F. Shepard
  • Patent number: 4435724
    Abstract: A single piece carrier which is for an integrated circuit device having oppositely extending leads and which utilizes opposed marginal tabs connected to torsional bar parts to hold the integrated circuit device within the carrier.
    Type: Grant
    Filed: September 10, 1981
    Date of Patent: March 6, 1984
    Assignee: Wells Electronics, Inc.
    Inventor: Donald E. Ralstin