Abstract: A relatively thin layer of extrinsic material formed on the top surface of a nearly intrinsic semiconductor substrate forms the detector area of an infrared detector device. A source region is provided along a portion of the perimeter of the detector area and is electrically coupled to the extrinsic detector area by means of an external connection. A drain channel is provided which is separated from the detector area by a gate region. The concentration of the extrinsic material in the detector area is sufficient for it to be at least a poor conductor. Thus, replacement electrons can flow from the source region into the extrinsic detector area via the external connection and electrical charge-neutrality can thereby be maintained at the extrinsic sites. The gate electrode forms a fringing field extending into the detector area which facilitates conduction from the detector area to the drain channel during the read-out process.

Abstract: Josephson junction integrated circuits of the current injection type and magnetically controlled type utilize a superconductive layer that forms both Josephson junction electrode for the Josephson junction devices on the integrated circuit as well as a ground plane for the integrated circuit. Large area Josephson junctions are utilized for effecting contact to lower superconductive layers and islands are formed in superconductive layers to provide isolation between the groundplane function and the Josephson junction electrode function as well as to effect crossovers. A superconductor-barrier-superconductor trilayer patterned by local anodization is also utilized with additional layers formed thereover. Methods of manufacturing the embodiments of the invention are disclosed.

Abstract: The present invention provides an improved Zener diode structure which avoids adverse structure causing leakage current or short circuits, for example. The pn junction is formed on a region of a first conductivity material below a window on the surface of the material. A second conductivity material fills the window to form the pn junction, and forms a sub-region at least at the edges of the window and extending substantially below the pn junction to maintain the pn junction far from the edges of the window.

Abstract: A thin film transistor comprising a substrate having source and drain electrodes formed thereon, a semiconductor layer making contact in part with the source electrode and in part with the drain electrode, a gate electrode, and a gate insulating layer positioned between the semiconductor layer and the gate electrode is disclosed. A portion of the drain electrode is held in overlapping relation to a portion of the gate electrode while a portion of the source electrode is spaced apart from said gate electrode.

Abstract: A semiconductor substrate which contains a buried grid-like region of enhanced concentration of an impurity type opposite to that of the semiconductor substrate; and method for the fabrication thereof which includes providing beneath the upper surface of a semiconductor substrate at a first depth a continuous region of a first impurity type which is the same as that of the semiconductor substrate and wherein at preselected isolated discontinuous locations beneath said surface the first impurity type is at a second depth beneath said surface which is greater than said first depth, and then providing beneath said first depth and substantially coincident with said second depth, a second impurity type opposite to that of the first type and at a dosage level lower than the dosage level of the first impurity type so as to provide a grid-like region of enhanced concentration of impurity type opposite to that of the semiconductor substrate for collecting excess minority carriers in the semiconductor substrate.

Abstract: A superconductive logic device incorporating at least one Josephson junction comprises two superconductive electrodes, that is, a base electrode and a counter electrode with a thin insulating layer therebetween. The counter electrode has an extension for receiving an input signal and another extension connected to a ground plane. The input signal current which is supplied from the counter electrode to the ground plane acts on the Josephson junction with a magnetic field, while, a bias current is supplied from the base electrode and flows through the Josephson junction to the ground plane.

Abstract: An optical bus arrangement is disclosed for interconnecting a plurality of circuit modules (15, 17 . . . ). It comprises a plurality of optical busses (25) each including a feeder waveguide (41) and a signal waveguide (43). Junctions (45) for controllably switching light from feeder to signal waveguide, and leaky regions (47) for detecting the status of the signal waveguide, are provided at regular intervals. Arrays of lasers/LEDs (33) at both ends constantly furnish light to the feeder waveguides.Each module has a plurality of input ports (27) each comprising a photodetector for detecting light from one leaky region, and a plurality of output ports (45) each comprising an electrode grating for controlling switching of light in one junction. Input ports and output ports are integrated portions of the chips. Thus, the optical waveguide switches disclosed have the specific feature of being partially incorporated as waveguide junction in a substrate (23), and partially as control electrodes integrated on a chip.

Abstract: A lead frame for an IC device includes a body element located at its center, the body element including recesses in its outer periphery in which the inner tips of the leads of the lead frame are fitted at predetermined positions. With such an arrangement, the leads are prevented from being deformed during steps of formation of the IC device.

Abstract: A semiconductor assembly comprising a flat disc-shaped semiconductor with terminals on opposite faces with an electrically conductive heat sink in electrical and thermal contact with each face. The semiconductor device and heat sinks are enclosed and maintained under compression by a rigid frame. The heat sinks are electrically insulated from each other and from the rigid frame by an insulating bond which secures these components together. Variations in compressive pressure holding the heat sinks in facing contact with the semiconductor device is compensated by a thermally responsive element positioned between each heat sink and the rigid frame in linear alignment with each other and the semiconductor device, whereby increases in temperature will expand the thermally responsive element to increase compression forces on the assembly of heat sinks and, semiconductor devices.

Abstract: A base region and a collector region of a bipolar transistor are interconnected through a hetero junction and forbidden band gap of the collector region is larger than that of the base region. When the transistor is made of a silicon base material, the collector region is made of oxygen containing polycrystalline silicon or amorphous silicon, whereas when made of a GaAs base alloy, the collector region is made of a mixed crystal of GaAs-AlAs.

Abstract: A light emitting diode constituted by a pair of semiconductor layers having a planar P-N junction therebetween, the semiconductor layers having at least one side surface extending transversely across the P-N junction and from which light is emitted in a direction parallel with the plane of the P-N junction, a pair of electrodes on the respective outer surfaces of the pair of semiconductor layers parallel with the plane of the P-N junction plane, at least one of the pair of electrodes covering an area less than the total area of the P-N junction and being located adjacent to the one side surface from which the light is emitted, the remainder of the area of the outer surface of the semiconductor layer not being covered by the electrode, and a light shielding member covering the remainder of the area of the outer surface of the semiconductor layer which is not covered by the one electrode.

Abstract: In a method of fabricating a semiconductor device having a V-groove insulating isolation structure with polycrystalline silicon filled in the groove of which internal surface is covered with an insulating film of silicon dioxide, the method according to this invention comprises the steps of selectively ion implanting an impurity material into a desired region of the polycrystalline silicon layer in order to give to this region a desired different type of electric conductivity relative to the polycrystalline silicon layer, followed by a selective annealing by an energy beam, such as laser, of a desired part of the polycrystalline silicon layer, including the region into which the impurity material has been ion implanted.

Abstract: The invention is a three-terminal transistor structure having five layers of materials that in combination provide conduction by high mobility carrier transport across the base in an energy valley above the conduction band. The conduction is by majority carrier tunneling injection from the emitter and transport at an upper valley level across the base. The resulting structure is capable of switching in times of 10.sup.-12 seconds.

Abstract: Disclosed is a tunnel diode consisting of an accumulation region of p-type GaSb and an accumulation region of n-type InAs separated by a thin layer of a quaternary compound consisting of InGaSbAs. Such a diode structure converts the interface between the two accumulation regions of p-type and n-type material from what would normally be an ohmic junction into a tunneling junction. Such a tunnel diode requires no heavy doping which is normally required for a tunnel diode.