Abstract: A method of generating a computer image wherein secondary raytrace vectors are calculated for the image after the image is rendered using rasterization. The secondary raytrace vectors are based on virtual camera angles that are stored during the rasterization process. The raytrace vectors can be calculated using the same processor as the rasterization, thereby providing greater consistency in the image. A metaprogrammed shader can also be applied to the generated image, wherein the shader uses the same processor as the raytrace and rasterization steps. The metaprogrammed shader allows the shader algorithm to be segmented for streamlined processing by the processor.

Abstract: A data buffering device which contains an input unit adapted to sequentially receive a two-dimensional array of data structures organized by an index pair with a first index stepwise traversing first-index values in a meandering manner defined by a first and a second meandering direction. The invention further includes a data buffering method, and a data processing method and device; each of which incorporates the above described features of the data buffering device.

Abstract: A method of generating displayable content is provided. The method includes obtaining a display package having a plurality of display elements defining a plurality of display frames. The method further includes rendering at least one selected group of the plurality of display elements. Each selected group is based on indicator information in the display package and comprises less than all of the plurality of display elements. Further included is saving a copy of each rendered selected group in a second display buffer. The method further includes rendering at least one display frame within the plurality of display frames such that at least a portion of the at least one rendered display frame comprises the saved copy of at least one rendered selected group. Further included is saving the at least one rendered display frame in a first display buffer that is different from the second display buffer.

Abstract: According to one embodiment, a graphics processor includes a decode request registering module which registers decode requests for image data items sequentially, a decode processing module which decodes and holds the image data items in a registration order of the decode requests, and a drawing module which acquires a decode result from the decode processing module according to a drawing request issued for each image data item and drawing the decode result. The registering module notifies an external device that a waiting state for the drawing request for the image data item has been established, in response to registration of the decode request for the image data item to ensure that the preparation of the drawing request for the image data item is performed in parallel with the decoding of the image data item.

Abstract: Example video composition systems and methods involve scaling each of multiple input video images with scaling factors to generate a plurality of scaled input video images each corresponding to one of the input video images. The scaled input video images are written into regions in a video storage unit. Video image signals are read out from the video storage unit on the basis of each of multiple video layout information pieces, the video layout information prescribing layout of the input video images when the input video images are composed. A composite video image is generated from the video image signals read out from the video storage unit for every video layout information pieces piece.

Abstract: A display (36) for reproducing an image intended for printing on a substrate using a set of inks, the image having a perceived color gamut when print it on the substrate, the display (36) including a light source (38) generating a set of at least three primary color (RGB), and a controller (42) combining the set of at least three primary color to substantially reproduce the image, wherein the at least three primary color define a viewed color gamut which substantially covers the perceived color gamut.

Abstract: One embodiment of the present invention sets forth a technique for displaying high-resolution images using multiple graphics processing units (GPUs). The graphics driver is configured to present one virtual display device, simulating a high-resolution mosaic display surface, to the operating system and the application programs. The graphics driver is also configured to partition the display surface amongst the GPUs and transmit commands and data to the local memory associated with the first GPU. A video bridge automatically broadcasts this information to the local memories associated with the remaining GPUs. Each GPU renders and displays only the partition of the display surface assigned to that particular GPU, and the GPUs are synchronized to ensure the continuity of the displayed images. This technique allows the system to display higher resolution images than the system hardware would otherwise support, transparently to the operating system and the application programs.

Abstract: One embodiment of the present invention sets forth a technique for improving the flexibility and programmability of a graphics pipeline by enabling full access to integer texture maps within a graphics processing unit (GPU). A new mechanism for loading and unloading integer texture images is disclosed that enables the shader units within the GPU to have full access to integer values stored within an integer image buffer in a GPU local memory. New integer formats are added to the graphics API that indicate that data should be loaded and processed without the prior art conversion to a floating-point representation, thereby enabling the use of these new integer data types.

Abstract: A method of generating a computer image wherein secondary raytrace vectors are calculated for the image after the image is rendered using rasterization. The secondary raytrace vectors are based on virtual camera angles that are stored during the rasterization process. The raytrace vectors can be calculated using the same processor as the rasterization, thereby providing greater consistency in the image. A metaprogrammed shader can also be applied to the generated image, wherein the shader uses the same processor as the raytrace and rasterization steps. The metaprogrammed shader allows the shader algorithm to be segmented for streamlined processing by the processor.

Abstract: A system, method, and computer program product are provided for broadcasting write operations in a multiple-target system. In use, a write operation is received at one of a plurality of apertures of an address space. Such write operation is then replicated to produce a plurality of write operations. To this end, the write operations may be broadcasted to a plurality of targets. At least one of the targets includes another one of the apertures that produces at least one additional write operation.

Abstract: A method and apparatus for distributing the workload of rendering an image where texture mapping is involved among multiple graphics processing units (GPUs) are provided. The method generally entails dividing a texture map among multiple GPUs, performing texture mapping in each GPU to render image data in each GPU's frame buffer, combining the image data from each frame buffer, and scanning out the combined image to a display.

Abstract: Systems and methods for graphics data management are described. One embodiment includes a graphics processing system comprising a texture management unit configured to organize texture map data according to a slice major format, wherein the texture map data spans at least one mip level. Furthermore, the graphics processing system comprises a texture cache, wherein the texture cache is coupled to the texture management unit and configured to receive the organized texture map data from the texture management unit.

Abstract: Methods and systems for compressing and decompressing data are described. A first value of N+1 bits and a second value of N+1 bits are reduced to strings of N bits each. The first and second strings of N bits are stored in a particular order relative to one another in a compression block. The particular order in which the first and second strings of N bits are stored in the compression block is used to derive a bit value that is then used in combination with one of the strings of N bits to reconstruct that string as N+1 bits.

Abstract: A reproducing apparatus includes a graphics processing unit that outputs graphics data, which forms a first screen image, in sync with a vertical sync signal and a pixel clock signal, a video decoder that outputs video data, which forms a second screen image, in sync with the vertical sync signal and the pixel clock signal, a blending process unit that executes a blending process for blending the graphics data, which is output from the graphics processing unit, and the video data, which is output from the video decoder, and a picture data output unit that outputs picture data, which is obtained by the blending process, to a display apparatus.

Abstract: A method and system for implementing transfers of texture data in a computer system. The method includes the step of accessing a first block of texture data in a low latency memory, the first block having a predetermined size and accessing a second block of texture data in high latency memory, the second block having the predetermined size. The first block of texture data is copied from the low latency memory to a transfer space in high latency memory having the predetermined size. The second block of texture data is written from the high latency memory to the low latency memory, wherein the second block overwrites the first block. What used to be the transfer space is now treated as the first block now placed in high latency memory, and what used to be the second block is now treated to be the new transfer space.

Abstract: One embodiment of the invention is a method for storing transformed vertex attributes that includes the steps of allocating memory space for a transform feedback buffer, selecting one or more transformed vertex attributes to store in the transform feedback buffer independently of any shader programs executing on any processing units in the graphics rendering pipeline, configuring the transform feedback buffer to store the one or more transformed vertex attributes, and initiating a processing mode wherein vertex data is processed in the graphics rendering pipeline to produce the transformed vertices, the attributes of which are then written to the transform feedback buffer. One advantage is that the transform feedback buffer can be used to store and access transformed vertices, without having to convert the vertex data to a pixel format, store the pixels in a frame buffer, and then convert the pixels back to a vertex format.

Abstract: A video decoder organizes and stores pixel lines of a reference picture into first and second memory devices. The video decoder then reads portions of a pixel block from the first and second memory devices and processes such a pixel block for generating a subsequent picture. By reading from the first and second memory device with time overlap, latency is minimized for faster video decoding.

Abstract: Provided is a system for compressing multiple-sample-anti-aliasing (MSAA) tile data in a computer graphics pipeline. The system includes a plurality of pixels configured as a tile, where the tile has a plurality of samples of descriptor data for the pixels. Multiple graphics data processing units configured to receive the plurality of samples contain a plurality of coverage masks, which correspond to covered subtiles and compression logic encodes the tile descriptor data for receipt by a buffer.

Abstract: A display controller coupled to a display device by way of a display interface and to a host device by way of a data port that includes a processor arranged to process executable instructions and associated data, a single memory device for storing the executable instructions and associated data and EDID corresponding to the display device, and a bridge portion coupling the single memory device to the host device by way of the data port, wherein the bridge portion is always in a powered on state thereby providing access to the single memory device by the host device even when the display controller is in a powered off state such as during a boot up process when the display controller is in the powered off state.

Abstract: A display controller coupled to a display device by way of a display interface and to a host device by way of a data port that includes a processor arranged to process executable instructions and associated data, a single memory device for storing the executable instructions and associated data and EDID corresponding to the display device, and a bridge portion coupling the single memory device to the host device by way of the data port, wherein the bridge portion is always in a powered on state thereby providing access to the single memory device by the host device even when the display controller is in a powered off state such as during a boot up process when the display controller is in the powered off state.