Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating, by an image sensor of a computing device, frame data comprising sub-frames of image pixel data. A first resource of the system-on-chip provides the frame data to a second resource of the system-on-chip. The frame data is provided to the second resource using a first data path included in the system-on-chip. The first resource provides a token to the second resource using a second data path included in the system-on-chip. A processor of the system-on-chip, uses the token to synchronize production of sub-frames of image pixel data provided by the first resource to the second resource and to synchronize consumption of the sub-frames of image pixel data received by the second resource from the elastic memory buffer.

Abstract: Disclosed is a system that receives a point cloud, and that generates a Bounding Volume Hierarchy (“BVH”) based on the point cloud data points. The BVH includes leaf nodes and parent nodes at one or more levels above the leaf nodes. The leaf nodes correspond to the point cloud data points. The system may receive input for adjusting a first set of elements of data points that are identified based on values specified for a second set of elements, and may locate those data points by traversing the BVH to arrive at a particular parent node that encompasses the values specified for the second set of elements. The system may then modify, based on the input, the first set of elements of a set of data points that correspond to a set of leaf nodes from the BVH that are directly or indirectly linked to the particular parent node.

Abstract: A method of executing an early-Z draw call in a graphics processing pipeline may include detecting a late-Z draw call in the pipeline, determining a compatibility of a depth comparison function of the early-Z draw call with a depth comparison function of the late-Z draw call, and speculatively executing a fragment of the early-Z draw call with a shader. The method may further include determining that the fragment of the early-Z draw call passes the depth comparison function of the early-Z draw call, and updating a depth buffer with a depth value for the fragment of the early-Z draw call. The method may further include determining that the fragment of the early-Z draw call provides a correct result, and forwarding the speculative shader result for the fragment to a next stage of the pipeline.

Abstract: A binning subsystem of a GPU includes a storage subsystem, a shader core to output first data via a first path, a selector to receive the first data via the first path, and to receive second data from the storage subsystem via a second path. The storage subsystem includes a binner unit and a control logic unit. The control logic unit causes the selector to transfer the first data or the second data to the binner unit. The binner unit may transfer binner output data to the shader core via a third path. The binner unit may transfer the binner output data to one or more subsequent stages of a graphics pipeline via a fourth path. The binner unit may transfer the binner output data to the storage subsystem via a fifth path. The control logic unit may control the binner unit such that the binner unit can be used for general purpose computation.

Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

Abstract: An apparatus includes at least one processor; and at least one non-transitory memory including computer program code; wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to perform: receive a scene description comprising data associated with a scene; place the data associated with the scene into data buffers and create command buffers; adapt the data placed within the data buffers and synchronize the data within the data buffers with information provided from local media or network media; signal information about the adaptation to update the command buffers that command a renderer; and render the scene using the data within the data buffers and the command buffers.

Abstract: Systems and methods are configured to adjust the timing of source frame compression in response to fluctuations in a variable frame rate at which source frames are rendered.

Abstract: The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure can determine a portion of a display area, where the portion of the display area is determined based on display content of the display area. Further, aspects of the present disclosure can communicate display information corresponding to the determined portion of the display area. Additionally, aspects of the present disclosure can update the display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also communicate the updated display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also render at least some display content of the display area corresponding to the determined portion of the display area. In some aspects, the updated display information can be based on the rendered display content of the display area.

Abstract: Disclosed techniques relate to grouping rays during traversal of a spatially-organized acceleration data structure (e.g., a bounding volume hierarchy) for ray intersection processing. The grouping may provide temporal locality for accesses to bounding region data. In some embodiments, ray intersect circuitry is configured to group rays based on the node of the data structure that they target next. The ray intersect circuitry may select one or more groups of rays for issuance each clock cycle, e.g., to bounding region test circuitry.

Abstract: The present disclosure relates to methods and apparatus for hybrid rendering of video/graphics content by a graphics processing unit. The apparatus can configure the graphics processing unit of a display apparatus to perform multiple rendering passes for a frame of a scene to be displayed on a display device. Moreover, the apparatus can control the graphics processing unit to perform a first rendering pass of the multiple rendering passes to generate a first render target that is stored in either an on-chip graphics memory of the GPU or a system of the display apparatus. The apparatus can also control the graphics processing unit to perform a second rendering pass to generate a second render target that is alternatively stored in the system memory of the display apparatus or on-chip graphics memory of the GPU.

Abstract: A parallel processing unit (e.g., a GPU), in some examples, includes a hardware scheduler and hardware arbiter that launch graphics and compute work for simultaneous execution on a SIMD/SIMT processing unit. Each processing unit (e.g., a streaming multiprocessor) of the parallel processing unit operates in a graphics-greedy mode or a compute-greedy mode at respective times. The hardware arbiter, in response to a result of a comparison of at least one monitored performance or utilization metric to a user-configured threshold, can selectively cause the processing unit to run one or more compute work items from a compute queue when the processing unit is operating in the graphics-greedy mode, and cause the processing unit to run one or more graphics work items from a graphics queue when the processing unit is operating in the compute-greedy mode. Associated methods and systems are also described.

Abstract: Disclosed are various embodiments for performing a join operation using a graphics processing unit (GPU). The GPU can receive input data including sequences or tuples. The GPU can initialize a histogram in a memory location shared by threads. The GPU can build the histogram of hash values for the sequences. The GPU can reorder the sequences based on the histogram. The GPU can probe partitions and store the results in a buffer pool. The GPU can output the results of the join.

Abstract: A primitive that triggers performance of a graphics operation for the entirety of a tile is included in the sequence of primitives for a sequence of rendering tiles being provided to subsequent stages of the graphics processing pipeline for processing at least one tile in advance of the tile to which the primitive that is to trigger a graphics processing operation for the entirety of the tile relates. If, subsequent to the starting of the processing of the primitive that performs a processing operation for the entirety of the tile, it is determined that no other primitives will be processed for the tile, at least one of the subsequent processing stages of the graphics processing pipeline is caused to stop performing processing in respect of the primitive that performs a processing operation for the entirety of the tile.

Abstract: Methods, systems, and computer-readable storage media for providing a simulated graph processing accelerator representative of a hardware-based graph processing accelerator, the simulated graph processing accelerator including a controller component, a set of producer components, and a final merge component; triggering execution of the simulated graph processing accelerator as a simulation of processing of a graph for one or more of breadth-first search (BFS), single source shortest path (SSSP), weakly connected components (WCC), sparse matrix-vector multiplication (SpMV), and PageRank (PR), execution including: generating request streams from each producer component, merging request streams to provide a merged request stream, inputting the merged request stream to a memory simulator, and processing, by the memory simulator, the merged request stream to simulate handling of requests in memory.

Abstract: A device having extended reality capabilities may capture a video feed including one or more video frames depicting an object that is visible in a field of view of the device. The device may provide the one or more video frames to a machine learning model that identifies the object and one or more parts of the object that are depicted in the one or more video frames. The device may obtain positional tracking information that represents a position and an orientation associated with the object relative to a coordinate space that corresponds to the field of view of the device. The device may obtain a workflow including a sequence of content items for visually inspecting the object using the extended reality capabilities of the device. The device may render digital content associated with the workflow using the extended reality capabilities of the device.

Abstract: An apparatus for calculating feature planes by hierarchically performing filter operation processing for input image data, comprises an operation unit configured to perform a convolution operation, a holding unit including memories configured to store image data and an operation result of the operation unit, a unit configured to receive the operation result, and write, out of the operation result, data of successive lines of the same feature plane in different memories of the memories and write data at the same coordinates of feature planes in the same layer in different memories of the memories, and a unit configured to read out the data of the successive lines from the different memories, read out the data at the same coordinates of the different feature planes in the same layer, and transmit the data to the operation unit.

Abstract: Disclosed herein are system, method, and computer program product embodiments for modifying graphics rendering by transcoding a serialized command stream. An embodiment operates by receiving a command configured to instruct an API to render a graphics element. The embodiment further operates by generating, based on the command, a transcoded command configured to instruct the API to render a modified graphics element by applying a set of modification factors to a portion of the command. Subsequently, the embodiment operates by transmitting the transcoded command to the API.

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type.

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of processing cores of a first type and a second type. A first set of processing cores of a first type perform multi-dimensional matrix operations and a second set of processing cores of a second type perform general purpose graphics processing unit (GPGPU) operations.

Abstract: One embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising compute unit including a hardware logic unit having dynamic precision fixed-point logic, the compute unit to receive a set of dynamic fixed-point tensors, compute, via the dynamic precision fixed-point logic, a right-shift value using an absolute maximum value within the set of dynamic fixed-point tensors and a dynamic range of the set of dynamic fixed-point tensors, right-shift data values within the set of dynamic fixed-point tensors based on the right-shift value, increment a shared exponent associated with the set of dynamic fixed-point tensors based on the right-shift value, perform a compute operation on the set of dynamic fixed-point tensors, and generate an output tensor via the compute operation on the set of dynamic fixed-point tensors.