Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of indices for each of a plurality of primitives. The apparatus may also determine a size of each of a plurality of primitive batches, each of the plurality of primitive batches including at least one primitive of the plurality of primitives. Additionally, the apparatus may divide, based on the determined size of each of the plurality of primitive batches, the plurality of primitives into the plurality of primitive batches. The apparatus may also distribute each of the plurality of primitive batches to each of a plurality of geometry slices, each of the plurality of geometry slices including one or more primitives of the plurality of primitives.

Abstract: This disclosure relates generally to method and system for tuning graphics processing unit (GPU) parameters of a GPU kernel. The disclosure proposes a combination of both heuristic and deterministic techniques for tuning GPU parameters of a GPU kernel to achieve optimal configuration of the GPU parameters. The proposed method and a system for tuning GPU parameters is based on deterministic techniques and heuristic techniques that includes capturing behavior of the GPU application by monitoring several GPU hardware counters that comprise several hardware resources and performance counters. The proposed tuning GPU parameters also implements a set of heuristic techniques to decide course of the tuning for various GPU parameters based on the captured behaviour of the GPU hardware counters.

Abstract: A method operating a Graphics Processing Unit (GPU) memory can be provided by accessing specified training parameters used to train a Deep Neural Network (DNN) using a GPU with a local GPU memory, the specified training parameters including at least a specified batch size of samples configured to train the DNN. A sub-batch size of the samples can be defined that is less than or equal to the specified batch size of samples in response to determining that an available size of the local GPU memory is insufficient to store all data associated with training the DNN using one batch of the samples. Instructions configured to train the DNN using the sub-batch size can be defined so that an accuracy of the DNN trained using the sub-batch size is about equal to an accuracy of the DNN trained using the specified batch size of the samples.

Abstract: Aspects of this disclosure provide techniques for generating a viseme and corresponding intensity pair. In some embodiments, the method includes generating, by a server, a viseme and corresponding intensity pair based at least on one of a clean vocal track or corresponding transcription. The method may include generating, by the server, a compressed audio file based at least on one of the viseme, the corresponding intensity, music, or visual offset. The method may further include generating, by the server or a client end application, a buffer of raw pulse-code modulated (PCM) data based on decoding at least a part of the compressed audio file, where the viseme is scheduled to align with a corresponding phoneme.

Abstract: Disclosed is neural network circuitry having a first plurality of logic cells that is interconnected to form neural network computation units that are configured to perform approximate computations. The neural network circuitry further includes a second plurality of logic cells that is interconnected to form a controller hierarchy that is interfaced with the neural network computation units to control pipelining of the approximate computations performed by the neural network computational units. In some embodiments the neural network computation units include approximate multipliers that are configured to perform approximate multiplications that comprise the approximate computations. The approximate multipliers include preprocessing units that reduce latency while maintaining accuracy.

Abstract: The disclosure discloses a method for preprocessing an image and a related electronic device. A current data frame captured through a camera is obtained by a pre-created drawing surface window called by a central processing unit (CPU) in response to a preview activating instruction of the camera. The current data frame is converted into a preview texture corresponding to the current data frame by the pre-created drawing surface window. The preview texture corresponding to the current data frame is sent to a graphics processing unit (GPU). The preview texture corresponding to the current data frame is processed by the GPU. The preview texture processed is sent by the CPU to an advanced driving assistance system (ADAS).

Abstract: A method and a system for Augmented Reality (AR) content creation is disclosed. The method includes creating a feature vector corresponding to each of a sequence of frames extracted from a video, based on a plurality of features captured. The method further includes determining a vector distance between each of two consecutive frames from the sequence of frames, based on the feature vector associated with each of the two consecutive frames. The method further includes dividing the video into a plurality of frames based on the determined vector distance. The method further includes creating a storyline based on an object and an action associated with the object in each of the plurality of frames, and generating a set of instructions for a user based on the storyline created for each of the plurality of frames and real-time video stream capturing a current state of a user environment.

Abstract: A method for presenting an image on a display device (100) includes modifying the image by applying a geometric transformation to the image so that an area of the image on the display device is presented to a viewer with higher density of pixels than that in the rest of the image (S18).

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Abstract: A method of initialising rendering at a graphics processing unit configured to perform safety-critical rendering, the method comprising: causing an instruction for initialising rendering of safety critical graphical data at the graphics processing unit to be provided to the graphics processing unit, said instruction comprising a request for response from the graphics processing unit; initialising a timer, said timer being configured to expire after a time period; and monitoring, during said time period, for a response from the graphics processing unit; determining, by a safety controller external to the graphics processing unit, that an initialisation error has occurred if no response is received from the graphics processing unit before the timer expires.

Abstract: A method of initialising rendering at a graphics processing unit configured to perform safety-critical rendering within a graphics processing system, the method comprising: generating configuration data for initialising rendering of safety critical graphical data at the graphics processing unit; receiving the configuration data for initialising rendering at the graphics processing unit; configuring the graphics processing unit in accordance with the configuration data for initialising rendering; determining whether the graphics processing unit is correctly configured in accordance with the configuration data; and determining, by a safety controller external to the graphics processing unit, that an initialisation error has occurred in response to determining that the graphics processing unit is not correctly configured in accordance with the configuration data.

Abstract: Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency, such as accuracy of learning, accuracy of prediction, speed of learning, performance of learning, and energy efficiency of learning. An array of processing elements performs flow-based computations on wavelets of data. Each processing element has a respective compute element and a respective routing element. Each compute element has processing resources and memory resources. Each router enables communication via wavelets with at least nearest neighbors in a 2D mesh. Stochastic gradient descent, mini-batch gradient descent, and continuous propagation gradient descent are techniques usable to train weights of a neural network modeled by the processing elements. Reverse checkpoint is usable to reduce memory usage during the training.

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes one or more processing units to provide a first set of shader operations associated with a shader stage of a graphics pipeline, a scheduler to schedule shader threads for processing, and a field-programmable gate array (FPGA) dynamically configured to provide a second set of shader operations associated with the shader stage of the graphics pipeline.

Abstract: An image processing apparatus of transferring a display image to a client machine, the display image being an image to be displayed on a display device associated with the client machine, the image processing apparatus including: a memory; and a processor coupled to the memory, the processor being configured to perform processing, the processing including: executing a first transfer process configured to transfer only moving image data as the display image; executing a second transfer process configured to transfer moving image data and still image data as the display image; and executing a control process configured to select either the executing of the first transfer process or the executing of the second transfer process, by using a frame rate of the display image and a state of a graphics processing unit (GPU) circuitry configured to perform a process related to an image.

Abstract: A method for profiling energy usage in graphics user interfaces (UI) in handheld mobile devices is disclosed, which includes quantifying the central processing unit (CPU) energy drain of each UI update, quantifying the graphics processing unit (GPU) energy drain of each UI update, quantifying the number of pixels changed due to each UI update, identifying an UI update that consumes energy drain but results in no pixel changes to the displayed frame as a graphics energy bug.

Abstract: Data structures, methods and primitive block generators for storing primitives in a graphics processing system.

Abstract: Methods and apparatus are provided for training an artificial neural network having a succession of neuron layers with interposed synaptic layers each having a respective set of N-bit fixed-point weights {w} for weighting signals propagated between its adjacent neuron layers, via an iterative cycle of signal propagation and weight-update calculation operations. Such a method includes, for each synaptic layer, storing a plurality p of the least-significant bits of each N-bit weight w in digital memory, and storing the next n-bit portion of each weight w in an analog multiply-accumulate unit comprising an array of digital memory elements. Each digital memory element comprises n binary memory cells for storing respective bits of the n-bit portion of a weight, where n?1 and (p+n+m)=N where m?0 corresponds to a defined number of most-significant zero bits in weights of the synaptic layer.

Abstract: Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block.

Abstract: An apparatus and method for multi-adapter and/or multi-pass encoding on dual graphics processors. For example, one embodiment of a processor comprises: a central processor integrated on a first die, the central processor comprising a plurality of cores to execute instructions and process data; an first graphics processor integrated on the first die, the first graphics processor comprising media processing circuitry to perform one or more preliminary lookahead operations on video content to generate lookahead statistics; an interconnect to couple the first graphics processor to a lookahead buffer, the first graphics processor to transmit the lookahead statistics over the interconnect to the lookahead buffer; wherein the lookahead statistics are to be used by a second graphics processor to encode the video content to generate encoded video.

Abstract: Methods and tiling engines for storing tiling primitives in a graphics processing system.