Patents Examined by Jack A. Lane
  • System and method for pre-fetching for pointer linked data structures
    Patent number: 6782454
    Abstract: A system and method are provided for efficiently prefetching data in a pointer linked data structure (140). In one embodiment, a data processing system (100) is provided including a processor (110) capable of executing a program, a main-memory (115) and a prefetch engine (175) configured to prefetch data from a plurality of locations in main-memory in response to a prefetch request from the processor. When the data in main-memory (115) has a linked-data-structure having a number nodes (145) each with data (150) stored therein, prefetch engine (175) is configured to traverse the linked-data-structure and prefetch data from the nodes. The prefetch engine (175) is configured to determine from data contained in a prefetched first node (145A) and an offset value a new starting address for a second node (145B) to be prefetched.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: August 24, 2004
    Assignee: Sun Microsystems, Inc.
    Inventor: Peter C. Damron
  • Control circuit to allow the use of an unbuffered DIMM in a system with a registered-DIMM-only chipset
    Patent number: 6782451
    Abstract: A control circuit to allow the use of an unbuffered DIMM in a system with a registered-DIMM-only chipset. The control circuit is for receiving an address signal and control signal outputted from the registered-DIMM-only chipset. Then, according to the DIMM installed into a memory module socket, the control circuit controls a transmitting module or buffering module to selectively output the address signal and control signal of the DIMM to the memory module socket. In a system with a registered-DIMM-only chipset, users can selectively use a registered DIMM or an unbuffered DIMM installed in the memory module socket according to actual condition.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: August 24, 2004
    Assignee: Asustek Computer Inc.
    Inventor: Jen-Ming Tseng
  • Memory access using system management interrupt and associated computer system
    Patent number: 6775734
    Abstract: A method and computer system for accessing memory through a system management interrupt is disclosed. The computer system contains a CPU, a chipset and a memory unit. When the CPU receives a system management interrupt signal, the computer system enters a system management mode. In one embodiment, a software interrupt is invoked for achieving the purpose of accessing the memory space beyond 1 Mbytes. A system management interrupt signal is generated by the chipset while a software interrupt service routine associated with the software interrupt is running. The memory space beyond 1 Mbytes can therefore be accessed while the system management interrupt handler routine relative to the system management interrupt signal is running.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: August 10, 2004
    Assignee: VIA Technologies, Inc.
    Inventor: Kuo-Chi Chang
  • Disk memory device
    Patent number: 6775744
    Abstract: When only one type of a memory having an access rate necessary for high-speed data processing is equipped with a subsystem so as to accommodate the entire amount of storage required for the subsystem, a considerable rise in costs occurs. Therefore, in order to keep the rise in cost to a minimum, high-speed memory of a storage capacity required for the high-speed processing and low-speed memory of a storage capacity that can be safely employed for low-speed processing are both equipped with the disk memory system. With this arrangement, the rise in costs can be kept to a minimum, and access time to the memory can be reduced. The performance of the disk memory system can be thereby improved.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: August 10, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Yagi, Xiaoming Jiang
  • Method and apparatus for allocating and using range identifiers as input values to content-addressable memories
    Patent number: 6775737
    Abstract: Methods and apparatus are disclosed for allocating and using range identifiers as input values to associative memories, especially binary content-addressable memories (CAMs) and ternary content-addressable memories (TCAMs). In one implementation, each of multiple non-overlapping intervals are identified with one of multiple unique identifiers. An indication of a mapping between the multiple non-overlapping intervals and the multiple unique identifiers is maintained. A particular unique identifier is determined from said multiple unique identifiers based on a value and said multiple non-overlapping intervals. A lookup operation is performed on an associative memory using the particular unique identifier to generate a result. One implementation uses a trie representation of a range tree of the intervals to derive the unique identifiers.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: August 10, 2004
    Assignee: Cisco Technology, Inc.
    Inventors: Priyank Ramesh Warkhede, William N. Eatherton, Shyamsundar N. Maniyar, Peram Marimuthu
  • Instruction pair detection and pseudo ports for cache array
    Patent number: 6775735
    Abstract: Embodiments are provided in which a first and second instructions are executed in parallel. A first and a second address are generated according to the first and second instructions, respectively. The first address is used to select a data cache line of a data cache RAM and a first data bank from the data cache line. The second address is used to select a second data bank from the data cache. The first and second data banks are outputted in parallel from the data cache RAM. An instruction pair testing circuit tests the probability of the first and second instructions accessing a same data cache line of the data cache RAM. If it is unlikely that the two instructions will access a same data cache line, the second instruction is refetched and re-executed, and the second data bank is not used.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: August 10, 2004
    Assignee: International Business Machines Corporation
    Inventor: David Arnold Luick
  • System and method for performing page table walks on speculative software prefetch operations
    Patent number: 6775747
    Abstract: A method and system are employed within a processor for performing page table walks on speculative software prefetch operations. The system includes a first fault register to store information associated with a faulting micro-op relating to a non-prefetch memory access operation and a second fault register to store information associated with a faulting micro-op relating to a prefetch memory access operation. Also included in the system is a first unit to determine whether a currently pending micro-op relates to a non-prefetch operation or a prefetch operation. The first unit is configured to drop the currently pending micro-op from a pipeline if (1) the currently pending micro-op relates to a prefetch memory access and (2) the currently pending micro-op has previously faulted.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: August 10, 2004
    Assignee: Intel Corporation
    Inventor: KS Venkatraman
  • Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors
    Patent number: 6775746
    Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: August 10, 2004
    Assignee: Intel Corporation
    Inventors: Nhon Quach, John Crawford, Greg S. Mathews, Edward Grochowski, Chakravarthy Kosaraju
  • System and method for replaying workload data in a data storage environment
    Patent number: 6775826
    Abstract: This invention is a system and method for replaying workload data that may be accessed in a data storage environment and then replayed for testing or other reasons. The invention has the capability to extract a trace of all I/Os to a data storage system for an extended period of time and then replay these I/Os back to that or another system. Variables may also be manipulated though the play back system to increase testing flexibility at a lower cost than actually introducing new physical variables.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: August 10, 2004
    Assignee: EMC Corporation
    Inventors: William Zahavi, Kenneth R. Coguen, Paul F. Hale, Andrew M. Shooman, Yeshayahu Hass
  • Data processing device
    Patent number: 6772314
    Abstract: There is provided a data processing device in which a ROM is mapped to an address space of a CPU only when a data storage region in a non-volatile memory is rewritten, to thereby facilitate rewriting the data storage region, and prevent a program storage region from being rewritten. A data processing device of the present invention is equipped with a CPU, a RAM, an address decoder, a flash memory and a mask ROM. When a data storage region in the flash memory is rewritten, the mask ROM is mapped while not being mapped in the other cases, whereby rewriting the data storage region is facilitated, and the program storage region is prevented from being rewritten.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: August 3, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Takashi Kashine
  • Data saving method and external storage device
    Patent number: 6772306
    Abstract: A data backup method, apparatus and computer program in a storage system including a first external storage device, a second external storage device, a service processor for inputting configuration information to the first storage device, wherein the first storage device includes a first controller for controlling a backup operation based on the configuration information, and a timer to be used to check a start timing of the backup operation.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: August 3, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyoshi Suzuki, Mamoru Toochi
  • Device and method for storing telephone entries
    Patent number: 6772275
    Abstract: A method and apparatus for storing entries in at least two separate storage areas of a non-volatile memory in a communications terminal, wherein the storage areas have fixed area boundaries, such that a dynamic redial list in the communications terminal is increased in a highly cost-effective fashion.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: August 3, 2004
    Assignee: Siemens Aktiengesellschaft
    Inventors: Hans-Georg Beerens, Alexander Hadt, Peter Paul Matthias Kisters, Ralf Ruether, Peter Scholz, Bernhard Slonina
  • System and method for preparation of workload data for replaying in a data storage environment
    Patent number: 6769054
    Abstract: This invention is a system and method for preparing workload data that may be accessed in a data storage environment and then replayed for testing or other reasons. The invention has the capability to prepare a trace of I/Os to a data storage system for an extended period of time for replaying these I/Os back to that or another system. Variables may also be manipulated through a preparation process and is particularly useful for customizing benchmarking tests, or consolidation, or trouble-shooting, or capacity planning.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: July 27, 2004
    Assignee: EMC Corporation
    Inventors: Adnan Sahin, Sachin More, Paul F. Hale
  • Instruction pair detection and pseudo ports for cache array
    Patent number: 6763421
    Abstract: Embodiments are provided in which a first and second instructions are executed in parallel. A first and a second address are generated according to the first and second instructions, respectively. The first address is used to select a data cache line of a data cache RAM and a first data bank from the data cache line. The second address is used to select a second data bank from the data cache. The first and second data banks are outputted in parallel from the data cache RAM. An instruction pair testing circuit tests the probability of the first and second instructions accessing a same data cache line of the data cache RAM. If it is unlikely that the two instructions will access a same data cache line, the second instruction is refetched and re-executed, and the second data bank is not used.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: July 13, 2004
    Assignee: International Business Machines Corporation
    Inventor: David Arnold Luick
  • File mapping system and related techniques
    Patent number: 6760823
    Abstract: A system for efficiently representing or “mapping” data so that it can be rapidly communicated to a back-up storage system from a primary processor or a shared storage device while at the same time allowing a backup system to backup files rather than devices is described.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: July 6, 2004
    Assignee: EMC Corporation
    Inventor: Neil F. Schutzman
  • Memory controller and a cache for accessing a main memory, and a system and a method for controlling the main memory
    Patent number: 6754778
    Abstract: A memory control system has a replacement detection/notification circuit for detecting occurrence of replacement of dirty entry in a cache and informing a memory controller of the detection, and a state control circuit for precharging the currently active page in a main memory when the memory controller is informed of the detection and a preceding access to the main memory attendant upon the replacement of dirty entry is completed. By precharging the active page in the main memory to return to the idle state when the preceding access attendant upon the replacement of dirty entry is completed, the succeeding access can be done only by activating the aimed page probably different from the above page. It is thereby obviated to return the activated page due to the preceding access to the idle state after a page miss occurs in the succeeding access.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: June 22, 2004
    Assignee: Fujitsu Limited
    Inventor: Taizo Sato
  • Process of operating a DRAM system
    Patent number: 6748483
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: June 8, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • Synchronous DRAM with control data buffer
    Patent number: 6738860
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: May 18, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • Process of using a DRAM with address control data
    Patent number: 6735668
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: May 11, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • Synchronous data system with control data buffer
    Patent number: 6735667
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: May 11, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait