Abstract: A cache coherency arrangement with support for pre-fetch ownership, to enhance inbound bandwidth for single leaf and multiple leaf, input-output interfaces, with shared memory space is disclosed. Embodiments comprise ownership stealing to enhance inbound bandwidth and to prevent or attenuate starvation of transactions or of an input-output interface for transactions.

Abstract: A controller for a double data rate synchronous dynamic random access memory (SDRAM) includes an address storage block comprising an address storage register for each of a plurality of priority levels for receiving a memory address of a request from an incoming command queue for each of a plurality of priority levels and a priority logic block coupled to the address storage block wherein the priority logic block comprises a first priority register for storing a register number field for each of the plurality of priority levels, a second priority register for storing a request valid field for each of the plurality of priority levels, and a third priority register for storing a state machine address field for each of the plurality of priority levels.

Abstract: A system for determining whether a memory is connected to a controller in a node of a data network. In order to utilize non-volatile memory elsewhere in the system, it is possible to eliminate the EEPROM which is normally connected to the controller. In order to indicate that the EEPROM is deliberately missing, a pull-up resistor connected to a voltage source is connected to the chip select signal line which normally runs between the controller and the EEPROM. If a high signal is received, the controller knows that the EEPROM is deliberately missing and that non-volatile memory will be provided elsewhere in the system.

Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.

Abstract: A system and method that provides an integrated circuit which includes a small on-chip buffer to store collected data, thereby shifting the burden of storing the majority of the collected data to external system memory, which is typically comprised of commodity memory chips. Since this external system memory is already in use by other system functions, utilizing such unused regions of this external memory increases overall hardware efficiency, while achieving lower ASIC manufacturing cost.

Abstract: In a computer system having memory in a processor and a plurality of attached heterogeneous disk storage subsystems, a system and method for managing the storage subsystems is provided. A volume of data is copied from a first disk storage subsystem from a first vendor to a second disk storage subsystem from a second vendor, of equal or greater capacity than the first disk storage subsystem, without requiring specialized hardware. An application program is able to access the data on the first disk storage subsystem while the data is being copied. The volume of data on the second disk storage subsystem is identified, within the computer system, as the volume of data on the first disk storage subsystem after the data is copied.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). To optimally run back to back cycles to the memory modules, a technique for providing de-rating parameters such that unnecessary latencies designed into the memory devices can be removed while the system is executing requests. By removing any unnecessary latency, cycle time and overall system performance can be improved.

Abstract: A system and method for managing utilization in a unidirectional stack. An application programming interface (API) is provided for facilitating user interaction with a stack management system associated with a computing environment such as an architectural simulator. The unidirectional stack is initialized via the API with respect to a fixed stack marker boundary, a stack base and a stack pointer. A high water mark is maintained for tracking the stack pointer's farthest location from the stack base during the execution of a program. When a program instruction is operable to access a stack location, one or more validity rules are applied to determine if the access operation is permissible. Where the program instruction is operable to modify the stack pointer, another set of validity rules are applied to determine if the stack pointer operation is permissible. User warning and optional return of program control are available when an invalid access operation or stack pointer operation is attempted.

Abstract: In a communicating method between data processing apparatuses using the Sockets API or the MPI API, the apparatus on the receiving side informs the apparatus on the sending side of a data length threshold, which makes the apparatus on the sending side to decide between sending data to a pre-registered pre-allocated buffer on the apparatus on the receiving side, or having the memory region that is the final destination of the data transfer registered and then sending the data to this memory region. When the length of the data to be sent does not exceed the threshold, sending to the pre-allocated buffer is selected, and the data transfer operation is completed by copying the received data from the pre-allocated buffer to the final destination of this transfer. In case the length of the data to be sent exceeds the threshold, the data is sent directly to the final destination of this transfer.

Abstract: A method and device for virtual memory support in a computer system using a mapping structure for address translation. Mapping indicators are associated with each process context and each mapping structure entry. When a context is demapped the mapping indicator associated with the context is changed and the mapping indicator in each mapping structure entry is employed to immediately invalidate further memory accesses for that context.

Abstract: A system and method are disclosed, according to which, the responsiveness of client/server-based distributed web applications operating in an object-oriented environment may be improved by cofetching read only commands. In an exemplary embodiment, the system and method are implemented by defining special preExecute and postExecute methods of cacheable commands. The preExecute method of a requested command may be invoked to execute secondary commands and then return them to the requesting client. The postExecute method of a requested command may be invoked to place the returned commands in a cache, along with the requested command. In this manner, a single request can be used to execute, retrieve and cache multiple related commands. Cofetched commands are designated by the application developer when the requested command and its associated methods are created, and may be chosen based on their anticipated use in conjunction with the requested command.

Abstract: A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two packed objects. In the preferred embodiment, the contents of a base register is combined respectively with each of two or more packed objects in an offset register.

Abstract: A cache management operation. In one embodiment, a first recall value for a first unit of data is generated, a second recall value for a second unit of data is generated, and the first and second recall values are compared. The unit of data having the higher recall value is stored in a first section of a storage device. The unit of data having the lower recall value is stored in a second section of a storage device. A greater amount of compression is performed on the unit of data having the lower recall value.

Abstract: A system provides mechanisms and techniques to retrieve trace data from a trace buffer residing in a data storage system. The software program operating on a processor within the data storage system operates in trace mode to produce trace data in the trace buffer upon occurrence of trace events. An event trace routine operates in response to a system call to access the trace buffer and return either a current value of a trace buffer pointer or the current trace buffer pointer as well as trace data read from the trace buffer beginning at a location and in an amount as specified in the system call to the event trace routine. The trace capture process can operate either within the data storage system or preferably on a remote host computer system to access trace data in the trace buffer in the data storage system by using the event trace routine.

Abstract: A method for dynamically adjusting a memory page-closing policy for computer systems employing various types of DRAM memory partitioned into one or more memory banks, and circuitry for implementing the method. In general, the method comprises monitoring memory accesses to memory banks and dynamically adjusting the memory page closing policy for those memory bank based on locality characteristics of its memory accesses so that memory latencies are reduced. In one embodiment, in response to memory requests from a computer system processor, memory accesses to the DRAM memory are made on a page-wise basis. As each memory page is accessed, a page-miss, page-hit or page-hit state is produced. Depending on the page access states, which generally will reflect the locality characteristics of (an) application(s) accessing the memory, a page-close set point is adjusted. When a timing count corresponding to the page exceeds the page-close set point, the memory page is closed.

Abstract: A system and method for managing stack utilization in a two-stack arrangement wherein the stacks are operable to grow towards each other. An application programming interface (API) is provided for facilitating user interaction with a stack management system associated with a computing environment such as an architectural simulator. Each of two stacks is initialized via the API with a stack base, a growth direction indicator and a stack pointer. High water marks are maintained for tracking each stack pointer's farthest location from the respective stack base during the execution of a program. When a program instruction is operable to access a location in either of the stacks, one or more validity rules are applied to determine if the access operation is permissible. Where the program instruction is operable to modify either of the stack pointers, another set of validity rules are applied to determine if the stack pointer operation is permissible.

Abstract: A method for managing storage reclamation on a tape management system is provided. The method allows the calculation of the optimum reclamation threshold value for a given system, thereby increasing the performance of the system drastically.

Abstract: A data processing system that provides a DMA Exclusive state that enables pipelining of Input/Output (I/O) DMA Write transactions. The data processing system includes a system processor, a system bus, a memory, a plurality of I/O components and an I/O processor. The data processing system further comprises operational protocol providing a pair of instructions/commands that are utilized to complete a DMA Write operation. The pair of instructions is DMA_Write_No_Data and DMA_Write With_Data. DMA_Write_No_Data is an address-only operation on the system bus that is utilized to acquire “DMA ownership” of a cache line that is to be written. The initial ownership of the cache line is marked by a weak DMA state (D1), which indicates that the cache line is being held for writing to the memory, but that the cache line cannot yet force a retry of snooped operations.

Abstract: An apparatus generates addresses for circular address buffers in a memory, in which a higher boundary of a circular buffer is implied from the current address. This approach is applied alone, and in combination with circular buffers which rely on an implied lower boundary to improve memory usage and flexibility in the design of circular buffers for integrated circuits. The dual mode address generator comprises inputs that receive a current address A, an address offset M, a buffer length L and a control signal; and logic configured to compute a first memory address for a buffer with an implied lower boundary and a second memory address for a buffer with an implied higher boundary in response to A, M, and L. One of the first and second memory addresses is provided in response to the control signal.

Abstract: A method and data processing system that supports pipelining of Input/Output (I/O) DMA Write transactions. An I/O processor's operational protocol is provided with a pair of instructions/commands that are utilized to complete a DMA Write operation. The instructions are DMA_Write_No_Data and DMA_Write_With_Data. DMA_Write_No_Data is an address-only operation on the system bus that is utilized to acquire ownership of a cache line that is to be written. The ownership of the cache line is marked by a weak DMA state, which indicates that the cache line is being held for writing to the memory, but that the cache line cannot yet force a retry of snooped operations. When each preceding DMA Write operation has completed or each corresponding DMA_Write_No_Data operation has been placed in a DMA Exclusive state, then the weak DMA state is changed to a DMA Exclusive state, which forces a retry of snooped operations until the write transaction to memory is completed.