Abstract: A method and apparatus for sharing a logic block between multiple peripheral/input/output I/O devices. A method and apparatus for generating a first interrupt in response to a request from one of the devices. A second interrupt is also generated. The second interrupt is recognized before the first interrupt, such that the second interrupt is handled first and causes the logic block to be configured for the requested device. Then the first interrupt is then handled in which the request to the desired device is serviced using the reconfigured hardware.

Abstract: A communications card for use with a computer system that provides a system for reducing unnecessary power consumption. When the system is enabled, the card prevents the computer system from detecting insertion of the card until cable necessary for communication is connected to the card. Once a cable is connected, two nodes within the card are coupled together allowing the computer system to detect the presence of the card. The computer system then activates the card by applying power thereto.

Abstract: An input interface using a multiplex type input circuit for selecting a desired one, as its output, of a plurality of input power signals in accordance with a control signal generated by a CPU and for supplying the selected input power signal to an electronic element unit.

Abstract: A system and method of synchronizing data transfers between two processors having different bus transactions by providing a buffer for storing the data and a control logic for dividing a concurrent address and data bus transactions into an address bus transaction followed by a data bus transaction. During a read operation, the requesting device is forced to wait for data availability before entering the data bus transaction. During a write operation, the data bus transaction is delayed by using a storage mechanism that effectively separates the address transaction from the data transaction. The present invention also provides direct memory access fly-by operations between an input/output device and a memory device. These operations are accomplished by isolating a secondary bus from the system bus and allowing the destination device to capture the requested data as soon as it is available on the system bus.

Abstract: An apparatus and method for reducing bottlenecks in a wireless communication system by allowing messages to be directly transmitted between wireless stations in certain circumstances instead of transmitting such messages through a centralized access point (AP) computer. Each AP computer maintains a connection list reflecting which stations are currently "connected" by wireless link to the AP by virtue of their being in its service area. As wireless stations move into and out of the service area for a particular AP, the AP updates this list, and any changes to the list are broadcast to all wireless stations in the service area. Thus, all stations (and the AP) have a current list of stations in the area. Each wireless station may periodically transmit a "keep alive" message to the AP, and thus the AP can determine which stations are in its area by noting which stations send such messages.

Abstract: A data transmission system between two system buses and a method therefor are capable of bi-directionally transmitting data between two bus systems whose word widths are different. The data word from a first system bus is converted to a data word width of a second system bus, and the converted data is outputted to the second system. The data word from the second system bus is converted to a data word width of the first system bus, and the converted data is outputted to the first system. The data transmission system includes first and second system interfaces, first and second FIFO buffers, first and second FIFO controllers, first and second latches, and first and second selectors correspondingly coupled between the first and second system buses to allow bi-directional transfer of data.

Abstract: An interrupt managing system for a computer system in which resources are managed by a real-time operating system. The interrupt managing system has managed interrupt storage unit in which information regarding interrupts to be managed by the real-time operating system is stored, interrupt disabling processing unit for reading out the information stored in the managed interrupt storage unit and disabling an interrupt designated by the information in order to perform exclusive control needed for system call processing, and interrupt enabling processing unit for enabling the disabled interrupt. According to the interrupt managing system, an asynchronous interrupt which does not have an influence on the resource management by an OS is enabled even during a system call processing and an interrupt which does not issue a system call can be processed without any delay.

Abstract: A method is provided of requesting use of a shared resource in a computer system. The method is suited to applications in which the device requesting use of the resource can predict the need for the resource before the need actually arises. A request for use of the resource is characterized by a latency between the request and a subsequent granting of the request. The latency has both a deterministic component and a non-deterministic component. In response to an initialization of the computer system, the deterministic component of the latency is measured. The use of the resource is then requested by the requesting device some predetermined time before the time at which the need for such use arises. The predetermined time corresponds to the deterministic component of the latency. The amount of local buffering required within the device is therefore chosen to accommodate only the random latency component.

Abstract: A processor subsystem includes a processor and a bus bridge conversion device for insertion into a slot of a host computer system. The processor operates according to a signaling protocol which is different than the signaling protocol of the computer system bus. The bus conversion device converts the signaling protocol of the system bus to the signaling protocol of the processor, and vice-versa. The bus conversion device includes logic for bus arbitration conversion, bus lock conversion, and cache coherency control. Logic is also included that converts incoming and outgoing requests so that the card may properly transact with other agents coupled to the bus.

Abstract: A flash electrically-erasable programmable read only memory (EEPROM) device including a flash EEPROM array having circuitry for controlling operations within the flash EEPROM array, a microprocessor for controlling operations external to the flash EEPROM array, circuitry for detecting when operations are taking place within the array, and circuitry for disabling the microprocessor during periods in which operations are taking place in the flash EEPROM array so that power use by the microprocessor is minimized.

Abstract: An enhanced system management mode (SMM) includes nesting of SMI (system management interrupt) routines for handling SMI events. Enhanced SMM is implemented in an computer system to support a Virtual System Architecture (VSA) in which peripheral hardware, such as for graphics and/or audio functions, is virtualized (simulated by SMI routines). Reentrant VSA/SMM software (handler) includes VSA/SMI routines invoked either by (a) SMI interrupts, such as from non-virtualized peripheral hardware such as audio FIFO buffers, or (b) SMI traps, such as from accesses to memory mapped or I/O space allocated to a virtualized peripheral function. SMI nesting permits a currently active VSA/SMI routine to be preempted by another (higher priority) SMI event. The SMM memory region includes an SMI header segment and a VSA/SMM software segment--the SMI header segment is organized as a quasi-stack into which nested SMI headers are saved.

Abstract: A computer system having an interconnection apparatus for connecting processors, peripherals and memories, the system including a plurality of electronic devices, and a multiple long bus structure with impedance elements disposed thereon for providing non-terminal termination points.

Abstract: Circuitry for performing a memory block write is described. The memory block includes b block words, each block word having t block bytes. Each block byte has s bits of memory. Each block byte is associated with at least two associated mask value bits. A constant register has at least s.times.t bits of memory arranged as t constant bytes, each constant byte storing a constant value, each constant byte associated with one block of every block word. The block write circuitry includes control circuitry for selecting one of a normal write function and a block write function in accordance with a block write signal. When the block write function is selected, the control circuitry stores the associated constant value in every nonmasked block byte substantially simultaneously in accordance with a value of the associated mask value bits.

Abstract: A method for generating an interrupt to a plurality of peripheral devices in a computer system, the computer system comprising a first bus, a bus bridge for coupling to the first bus and for interfacing to a second bus, a second bus coupled to the bus bridge, and a plurality of peripheral devices connected to the second bus. The method comprises activating a source port in the bus bridge to configure the source port in the bus bridge for a transfer. The bus bridge receives from the first bus and stores an encoded interrupt vector in a register of the source port. The encoded interrupt vector is indicative of one or more interrupt requests at a target peripheral device. The bus bridge transmits an address/data pair to a destination port of the target peripheral device. The address/data pair includes an address of the destination port and encoded interrupt vector received from the first bus.

Abstract: A communications protocol operable in a multi-processor transmitter environment that facilitates communication between the microprocessors is provided. The transmitter includes a sensor module having a sensor microprocessor and a sensor memory. The sensor module digitizes and compensates sensed process variables. The transmitter also includes an electronics module having an electronics microprocessor wherein the sensor and electronics microprocessors each include individually controllable output pins and individually readable input pins. The sensor and electronics microprocessors are connected by an interface having a bus system. The communications protocol comprises a set of instructions formed into procedures. The procedures include a sensor update procedure; a receive data procedure; a send data procedure; a send command procedure; an indexed read procedure; and a read memory direct procedure.

Abstract: A bus structure for interconnecting the modules of an industrial automation controller includes DATA lines and associated control lines that enable interface circuits on each module to transfer frames of data. Modules connected to the bus structure support data transfers of differing widths and differing speeds, and interface circuits within each module automatically adapt to data width and speed differences between communicating modules. During a first bus cycle of each transfer, sending and receiving modules negotiate a bus width and clock speed to be used for the transfer by asserting their respective width and speed codes onto a set of wired-or status lines. After the first bus cycle, the status lines are then used for communicating alternate functions between the participating modules.

Abstract: A computer system which includes a circuit to monitor the PCI bus master grant lines and provide a disk drive activity signal if an appropriate grant line is activated. The PCI bus master grant lines are combined with mask signals, so that the grant lines not associated with a PCI bus master such as a SCSI controller are ignored. If an unmasked grant line is activated, a down counter is loaded. While the counter is at a non-zero value, a disk drive activity signal is provided. This disk drive activity signal is combined with other disk drive activity signals to drive the disk drive activity LED.

Abstract: An improved bus arbitration system comprising an information bus, first and second bus masters connected to the bus and a bus arbiter for controlling ownership of the bus. The first bus master is adapted to perform speculative pre-fetching and has a first REQ signal for requesting ownership of the bus and an SP signal for indicating when a bus ownership request is for a speculative pre-fetch. The second bus master has a second REQ signal for requesting ownership of the bus. The bus arbiter is configured such that when the first bus master asserts its REQ signal and its SP signal and the second bus master asserts its REQ signal, the bus arbiter assigns higher priority to the second bus master in response to the SP signal.

Abstract: An interface unit connected between a first bus and a second bus, the first bus having connected thereto a memory system and the second bus having connected thereto a plurality of devices which perform read operations directed at the memory system, the interface unit including a buffer memory having an input that is electrically coupled to the first bus for receiving data that is sent from the memory system over the first bus and an output that is electrically coupled to the second bus for delivering data to the second bus for transfer to a requesting device, the requesting device being one of the plurality of devices; a plurality of prefetch size registers equal in number to the plurality of devices, wherein each of the plurality of prefetch size registers stores a number for a different corresponding one of the plurality of devices, wherein the number stored in each of the plurality of prefetch size registers specifies an amount of data that is prefetched from memory in response to a data read request from

Abstract: A method and apparatus for providing serial interface capability that detects whether another communications system transmits or receives data on a particular node, and in response, automatically selects to either receive or transmit data on that node. An interface circuit is included that determines whether a particular node is coupled to a receiver circuit or a driver circuit based on the voltage level detected on that node. Based on this determination, the interface circuit is configured to either transmit or receive data on that node. This allows the interface circuit to interact with differently configured communications systems without the need for special cables, or for user intervention.