Abstract: An interrupt polling unit included within a bus interface unit of a microprocessor is provided. The interrupt polling unit causes an interrupt acknowledge bus transaction to occur. If an interrupt controller receiving the interrupt acknowledge bus transaction returns an interrupt vector indicative of an interrupt service routine, then the microprocessor executes the interrupt service routine. The number of interrupt acknowledge bus transactions associated with the interrupt is reduced from two to one. In one embodiment, the interrupt polling unit causes an interrupt acknowledge bus transaction to occur when the microprocessor is performing a task switch. The task switch may be performed by hardware included within the microprocessor or, alternatively, by software executing upon the microprocessor.

Abstract: A desktop computer system having the capability to suspend and resume the state of the computer system. The suspended system state is saved to the system hard file such that system power may be removed, effectively allowing a system suspend requiring no power from the power supply.

Abstract: A device driver architecture that couples an operating system to a computer interface of a controller device that includes a plurality of functional sub-elements. The device driver includes a plurality of operating system interface objects each presenting an operating system interface (OSI) to the operating system, a plurality of computer interface objects each providing for the generation of programming values to be applied to the computer interface to establish the operating mode of a respective predetermined subelement of the controller device, and a device driver library of processing routines callable by each of the plurality of operating system interface objects to process data and generate calls to the plurality of computer interface objects in predetermined combinations. The device driver library enables the selection of an execution contexts within which to define the generation and application of the programming values to the computer interface.

Abstract: The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a common system bus. The arbitration system includes a plurality of distributed bus arbiters which receives the bus requests from the sub-systems and independently determine the next bus master. The arbitration protocol enables the arbitration process to be eliminated from the critical timing path thereby allowing the system to operate at the maximum system clock frequency possible for a given integrated circuit (IC) technology to reduce overall system clock latencies. Any change among the sub-systems during an arbitration clock cycle is based on any system bus request(s) which are active during a clock cycle immediately preceding the arbitration clock cycle, and is independent of any system bus request(s) asserted during the arbitration clock cycle. In addition, the arbitration protocol treats a current bus master, i.e.

Abstract: An integrated circuit for providing multiple configuration modes in a multi-funtion intelligent bridge that includes an integrated processor. A first circuit, coupled to a first external bus, for selectively generating retry cycles onto the first external bus in response to a retry signal is provided. A second circuit, coupled to a local processor, for selectively resetting a local processor that is integrated in the intelligent bridge in response to a reset signal is provided. The first and second circuit, in conjunction with the retry signal and the reset signal, selectively provides one of a multiple number of configuration reset modes for the multi-function intelligent bridge.

Abstract: A system and method for reducing the time required to access peripheral devices or to perform peripheral device operations in a multiple bus architecture or hierarchical bus structure environment. A memory device is used to remember which addresses generated responses on which busses. The memory device is accessed in subsequent operations to eliminate the procedure for determining which bus is attached to the desired peripheral.

Abstract: A system for upgrading a personal computer includes a motherboard having upgrade sockets for upgrading the CPU and the clock oscillator without the need to remove any components. The system includes sensing circuitry for detecting the type of component plugged into the upgrade socket and circuitry for disabling the upgraded component. In addition, the system includes software for reconfiguring various signals depending on the particular upgrade plugged into the upgrade socket. By providing a system that can be upgraded by merely inserting a newer components, upgrades can be performed rather quickly. In addition, the upgrade system allows the end user a plurality of upgrade options while at the same time allows the end user to take advantage of declining CPU prices.

Abstract: A system and method for virtualizing external pins and their internal functions within a microprocessor employing an operating system independent interrupt and N subhandlers to virtual the equivalent functions of the pins ordinarily performed by extrinsic circuitry internal to the microprocessor.

Abstract: Several designs of a stage for use in a FIFO pipeline are disclosed. Each stage includes a latch that is capable of latching a data element and capable of transitioning between a transparent state and an opaque state. The stages also include a control circuit capable of announcing the availability of the data element to the next stage as soon as the data element has propagated through the latch and without any latching or unlatching action of the latch prior to the announcement of the availability of the data element. In other words, if the latch of a stage is transparent and receives a signal Ri from the previous stage, the control circuit of the stage generates signal Ro after receiving signal Ri, thus enabling the next stage to latch the data element before the current stage has itself latched that data element.

Abstract: A leaky bucket checker which combines synchronous updates with event driven asynchronous updates triggered by packet arrivals. A synchronous update is performed exactly as an event-driven update by assuming that a packet of length zero has arrived at the time of the update. These updates are performed in a round robin fashion on each connection. Therefore, assuming that one such update can be performed in each clock tick, the maximum bit representation of the last update time state variable can be limited to N bits for 2.sup.N total connections. Given the reduced processing and storage costs, a great number of network connections and leaky bucket checkers is possible.

Abstract: A computer system (6,7) includes first and second I/O circuits (932, 934), 51, 97 first and second buses (904, 83) respectively coupled to the first and second I/O circuits (932, 934), 51, 97 a memory (106), a third bus (104) coupled to the memory (106), and first and second bus interface circuits (902, 6920) connected between the third bus (104) and the first and second buses (904, 83) respectively. A direct memory access (DMA) controller (910) is coupled to the first bus (904) and to the first bus interface circuit (902), and a serial communications circuit (7010, 6910, 7020) is connected between the DMA controller (910) and the second bus interface circuit (6920). As an example, in the present invention a single DMA controller may be used to provide DMA capability to both a notebook computer and a docking station, using an related information between the DMA controller and a requesting device in the docking station. Other devices, systems and methods are also disclosed.

Abstract: An information processing system comprises a processor, a first bus for conducting signals in accordance with a first bus protocol that does not support I/O address signals; a second bus for conducting signals in accordance with a second bus protocol that supports input/output (I/O) address signals; and a bridge circuit for coupling the first bus to the second bus. The processor includes a circuit for emitting address signals and an address type signal directed to a selected peripheral device. The bridge circuit comprises a filter for determining whether the address signal emitted by the processor corresponds to a peripheral device coupled to a bus subordinate to the bridge circuit; and a translation circuit, coupled to the filter, for translating signals in accordance with the first bus protocol to signals in accordance with the second bus protocol for transmission to the selected peripheral device.

Abstract: A logic LSI chip includes a CPU, a bus, a memory, and a multiplier. In addition, the logic LSI chip includes a command signal line for transferring, from the CPU to the multiplier, a command regarding a multiplication instruction relating to data read out, while the data is being read out from the memory, so that the multiplier can fetch the data directly from the bus. While the CPU is reading data from the memory, therefore, a command of a multiplication instruction relating to data read out is transferred from the CPU to the multiplier. A bus cycle control circuit receives a state signal from the multiplier when the multiplier is executing a repetitional operation and the bus cycle control circuit responds to the state signal by signalling the CPU to delay issuance of a succeeding command to the multiplier.

Abstract: In a data processing system having an operating system and a power management controller coupled to one or more power-managed devices, each of the power-managed devices is assigned a device identifier. An architected power-managed device select register and an architected power mode select register are provided within the data processing system. To modify a power mode of a power-managed device, the operating system writes a selected one of the device identifiers to the architected power-managed device select register for selecting an identified one of the power-managed devices. Thereafter, the operating system writes a power mode identifier to the architect power mode select register for selecting one of a plurality of power modes within the selected power-managed device. The device identifier and the power mode identifier are translated into control signals for the power management controller within the data processing system.

Abstract: A delay gate is provided within a control unit to delay the reset signal by a predetermined period of time to monitor the time at which the reset signal passes through the busline. If the busline length exceeds a prescribed length, then an LED is turned on. Or a resistance proportional to the length of a duplex bus signal line is connected to each connecting portion, a reference resistance is provided internally of the control unit and one of the duplex signal buslines of the connecting portion is grounded while the other is connected through the reference resistance to a reference power supply to compare the potential difference between the reference resistance and the connecting point of the duplex signal busline with a reference signal so that, when the busline length exceeds a prescribed value, the LED is turned on.

Abstract: A portable computer comprising a PCMCIA card connector, a PCMCIA controller, a multimedia display controller, a moving-picture bus, a system bus, and a switching control circuit. The PCMCIA controller controls transfer of data to and from a PC card connected to the PCMCIA card connector. The multimedia display controller can process moving-picture data to display moving pictures. The moving-picture bus connects the PCMCIA controller and the multimedia display controller, for supplying moving-picture data only. The switching control circuit is incorporated in the PCMCIA controller, for connecting the PCMCIA card connector to the moving-picture bus or to the system bus.

Abstract: A method and apparatus for providing an external indication of internal cycles in a data processing system (10) in order to more easily debug software being executed by data processing system (10). In one embodiment, data processing system (10) provides cycle type signals (14) external to data processing system (10). The cycle type signals (14) can be used to determine a variety of information about the activity and bus cycles being performed within data processing system (10), activity which is not readily discernible except by way of the cycle type signals (14). In some cases the information provided by the cycle type signals (14) is sufficient for debug purposes; in other cases, information from additional signals, e.g. the address type signals (15) and the read/write signal (19) may also be required.

Abstract: A device adapter maintains a device polling table in memory that can be dynamically changed in response to disk drive device failures and is updated with each poll so that failed devices can be quickly deleted from the table and alternate device polling mapping can be achieved. A system reconfiguration is not necessary to implement the modifications to the system processing. The device adapter is capable of a greater variety of processing tasks than is conventional, including determining cylinder head position and copying data that otherwise would be performed by a control unit.

Abstract: A speculative instruction queue for a superscalar processor of the type having a variable byte-length instruction format, such as the X86 format, is organized as a 16-byte FIFO. The head of the queue is always the beginning byte of an X86 instruction, and the queue always shifts by one or more X86 instruction boundaries as X86 instructions are decoded and dispatched. Each byte position within the queue includes a valid bit for indicating whether the byte position within the queue contains valid information, the raw X86 instruction byte as originally fetched from an instruction source and stored within a preceeding cache, and a group of predecode bits assigned to the raw X86 instruction byte when initially pre-fetched and cached, and which predecode bits indicate the starting byte, ending byte, and the opcode byte of an X86 instruction, as well as the number of internal RISC-like operations into which the corresponding X86 instruction is mapped.

Abstract: The invention relates to a method and a circuit for rearranging output data of a variable-length decoder (VLD).