Abstract: A method of manufacturing a laterally diffused metal oxide semiconductor (LDMOS) device, and an integrated circuit associated therewith. The method includes forming a lightly-doped source/drain region with a first dopant, the lightly-doped source/drain region located between first and second isolation structures. The method further includes creating a gate over the lightly-doped source/drain region. In one advantageous embodiment of the present invention, the method further includes diffusing a second dopant at least partially across the lightly-doped source/drain region and under the gate to form a first portion of a channel.

Abstract: A method of manufacturing a laterally diffused metal oxide semiconductor (LDMOS) device, and an integrated circuit associated therewith. The method includes forming a lightly-doped source/drain region with a first dopant, the lightly-doped source/drain region located between first and second isolation structures. The method further includes creating a gate over the lightly-doped source/drain region. In one advantageous embodiment of the present invention, the method further includes diffusing a second dopant at least partially across the lightly-doped source/drain region and under the gate to form a first portion of a channel.

Abstract: A crystallization method includes providing a substrate having a silicon thin film; positioning a laser mask having first to fourth blocks on the substrate, each block having a periodic pattern including a plurality of transmitting regions and a blocking region; and crystallizing the silicon thin film by irradiating a laser beam through the laser mask. A polycrystalline silicon film crystallized by this method is substantially free from a shot mark, and has uniform crystalline characteristics.

Abstract: A method of forming a capacitor includes forming a first capacitor electrode over a substrate. A substantially crystalline capacitor dielectric layer is formed over the first capacitor electrode. The substrate with the substantially crystalline capacitor dielectric layer is provided within a chemical vapor deposition reactor. Such substrate has an exposed substantially amorphous material. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the substantially crystalline capacitor dielectric layer relative to the exposed substantially amorphous material, and the polysilicon is formed into a second capacitor electrode.

Abstract: A conductor-filled damage propagation barrier is formed extending into a low-k dielectric layer between a fuse and an adjacent circuit element for preventing propagation of damage during a fuse blow operation. Conductor material filling the damage propagation barrier is formed from the same conductor layer as that used to form an interconnect structure.

Abstract: A MEMS switch fabrication process and apparatus inclusive of a bulbous rounded surface movable contact assembly that is integral with the switch movable element and achieving of long contact wear life with low contact electrical resistance. The disclosed process is compatible with semiconductor integrated circuit fabrication materials and procedures and includes an unusual photoresist reflow step in which the bulbous contact shape is quickly defined in three dimensions from more easily achieved integrated circuit mask and etching-defined precursor shapes. A plurality of differing photoresist materials are used in the process. A large part of the contact and contact spring formation used in the invention is accomplished with low temperature processing including electroplating. Alternate processing steps achieving an alloy metal contact structure are included. Use of a subroutine of processing steps to achieve differing but related portions of the electrical contact structure is also included.

Abstract: The invention discloses a switching element of a pixel electrode for a display device and methods for fabricating the same. A gate is formed on a substrate. A first copper silicide layer is formed on the gate. An insulating layer is formed on the first copper silicide layer. A semiconductor layer is formed on the insulating layer. A source and a drain are formed on the semiconductor layer. Moreover, a second copper silicide layer is sandwiched between the semiconductor layer and the source/drain.

Abstract: Provided is a surface emitting laser or the like capable of suppressing horizontal misalignment between the surface relief structure and the current confining structure to make higher the precision of the alignment, to thereby obtain single transverse mode characteristics with stability. The surface emitting laser having a semiconductor layer laminated therein includes: a first etching region formed by etching a part of the upper mirror; and a second etching region formed by performing etching from a bottom portion of the first etching region to a semiconductor layer for forming a current confining structure, in which a depth of the second etching region is smaller than a depth of the first etching region.

Abstract: In a semiconductor integrated circuit device and a method of formation thereof, a semiconductor device comprises: a semiconductor substrate; an insulator at a top portion of the substrate, defining an insulator region; a conductive layer pattern on the substrate, the conductive layer pattern being patterned from a common conductive layer, the conductive layer pattern including a first pattern portion on the insulator in the insulator region and a second pattern portion on the substrate in an active region of the substrate, wherein the second pattern portion comprises a gate of a transistor in the active region; and a capacitor on the insulator in the insulator region, the capacitor including: a lower electrode on the first pattern portion of the conductive layer pattern, a dielectric layer pattern on the lower electrode, and an upper electrode on the dielectric layer pattern.

Abstract: The invention involves the integration of curved micro-mirrors over a photodiode active area (collection area) in a CMOS image sensor (CIS) process. The curved micro-mirrors reflect light that has passed through the collection area back into the photo diode. The curved micro-mirrors are best implemented in a backside illuminated device (BSI).

Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.

Abstract: A method of forming a contact structure with a contact spacer and a method of fabricating a semiconductor device using the same. In the method of forming a contact structure, an interlayer dielectric layer is formed on a semiconductor substrate. The interlayer dielectric layer is patterned, thereby forming a contact hole for exposing a predetermined region of the semiconductor substrate. A contact spacer is formed on a sidewall of the contact hole using a deposition method having an inclined deposition direction with respect to a main surface of the semiconductor substrate. The deposition direction may be set between the main surface and a normal with respect to the main surface. Further, there is provided a method of fabricating a semiconductor device using the method of forming the contact structure.

Abstract: Bipolar power semiconductor component comprising a p-type emitter and more highly doped zones in the p-type emitter, and production method. The invention relates to a bipolar power semiconductor component comprising a semiconductor body (1), in which a p-doped emitter (8), an n-doped base (7), a p-doped base (6) and an n-doped main emitter (5) are arranged successively in a vertical direction (v). The p-doped emitter (8) has a number of heavily p-doped zones (82) having a locally increased p-type doping.

Abstract: A method of manufacturing a semiconductor device includes forming a trench in an interlayer dielectric film on the semiconductor substrate, the trench reaching a semiconductor substrate and having a sidewall made of silicon nitride film; depositing a gate insulation film made of a HfSiO film at a temperature within a range of 200 degrees centigrade to 260 degrees centigrade, so that the HfSiO film is deposited on the semiconductor substrate which is exposed at a bottom surface of the trench without depositing the HfSiO film on the silicon nitride film; and filling the trench with a gate electrode made of metal.

Abstract: A method of manufacturing light-emitting diode device has steps of isolating a light-emitting side of an LED chip from a wire-bonding region by disposing partition panels on the wire-bonding region and coating phosphors on the light-emitting side of the LED chip in a phosphor-coating process. The method can be applied to manufacturing LED device having a flip chip structure or a vertical chip structure. According to the method, a white LED device can be directly manufactured without adopting a phosphor package technique, and thereby a whole package process of the white LED device is simplified.

Abstract: Disclosed are embodiments of a semiconductor structure with a partially selfaligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole.

Abstract: A method of manufacturing light-emitting diode device has steps of isolating a light-emitting side of an LED chip from a wire-bonding region by disposing partition panels on the wire-bonding region and coating phosphors on the light-emitting side of the LED chip in a phosphor-coating process. The method can be applied to manufacturing LED device having a flip chip structure or a vertical chip structure. According to the method, a white LED device can be directly manufactured without adopting a phosphor package technique, and thereby a whole package process of the white LED device is simplified.

Abstract: A method of manufacturing light-emitting diode device has steps of isolating a light-emitting side of an LED chip from a wire-bonding region by disposing partition panels on the wire-bonding region and coating phosphors on the light-emitting side of the LED chip in a phosphor-coating process. The method can be applied to manufacturing LED device having a flip chip structure or a vertical chip structure. According to the method, a white LED device can be directly manufactured without adopting a phosphor package technique, and thereby a whole package process of the white LED device is simplified.

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

Abstract: A backside illuminated image sensor comprises a sensor layer having a plurality of photosensitive elements of a pixel array, an oxide layer adjacent a backside surface of the sensor layer, and at least one dielectric layer adjacent a frontside surface of the sensor layer. A color filter array is formed on a backside surface of the oxide layer, and a transparent cover is attached to the backside surface of the oxide layer overlying the color filter array. Redistribution metal conductors are in electrical contact with respective bond pad conductors through respective openings in the dielectric layer. A redistribution passivation layer is formed over the redistribution metal conductors, and contact metallizations are in electrical contact with respective ones of the respective redistribution metal conductors through respective openings in the redistribution passivation layer. The image sensor may be implemented in a digital camera or other type of digital imaging device.