Abstract: An object cutting method which can reliably remove particles remaining on cut sections of chips is provided. An expandable tape 23 is electrically charged in a state where a plurality of semiconductor chips 25 obtained by cutting a planar object to be processed along a line to cut are separated from each other on the expandable tape 23. This electric action causes particles remaining on cut sections of the semiconductor chips 25 to eject therefrom even when a molten processed region is formed in the cut sections. Therefore, particles remaining on the cut sections of the chips 25 can reliably be removed.

Abstract: A backside illuminated image sensor comprises a sensor layer implementing a plurality of photosensitive elements of a pixel array, an oxide layer adjacent a backside surface of the sensor layer, and at least one dielectric layer adjacent a frontside surface of the sensor layer. The sensor layer further comprises a plurality of backside trenches formed in the backside surface of the sensor layer and arranged to provide isolation between respective pairs of the photosensitive elements. The backside trenches have corresponding backside field isolation implant regions formed in the sensor layer, and the resulting structure provides reductions in carrier recombination and crosstalk between adjacent photosensitive elements. The image sensor may be implemented in a digital camera or other type of digital imaging device.

Abstract: Provided is a surface emitting laser or the like capable of suppressing horizontal misalignment between the surface relief structure and the current confining structure to make higher the precision of the alignment, to thereby obtain single transverse mode characteristics with stability. The surface emitting laser having a semiconductor layer laminated therein includes: a first etching region formed by etching a part of the upper mirror; and a second etching region formed by performing etching from a bottom portion of the first etching region to a semiconductor layer for forming a current confining structure, in which a depth of the second etching region is smaller than a depth of the first etching region.

Abstract: A step of forming a first auxiliary groove in a semiconductor element structure provided on a semiconductor substrate, a step of forming a second auxiliary groove in the semiconductor element structure, and a step of dividing the semiconductor substrate and the semiconductor element structure in a direction along the first auxiliary groove and the second auxiliary groove are provided, and in the dividing direction, a plurality of the second auxiliary grooves are arranged spaced apart from each other, and at least two first auxiliary grooves are arranged spaced apart from each other between at least a pair of adjacent second auxiliary grooves, and in the dividing step, a separation region interposed between the two first auxiliary grooves is divided, so as to improve such accuracy and suppress the problems such as a damage of the end surface due to cleavage of the substrate.

Abstract: A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.

Abstract: A method for forming a cylindrical stack capacitor structure. A semiconductor substrate is provided. Storage node structures are formed in a memory cell region. A dielectric layer is formed overlying the storage node structures. A patterning and a first etching process expose the storage nodes. A polysilicon layer and a rugged polysilicon layer are formed overlying the exposed storage nodes. The memory cell region is masked, exposing a peripheral region. A chemical dry etch process removes the rugged polysilicon and the polysilicon layers in the peripheral region. The rugged polysilicon and the polysilicon layers are planarized followed by a dielectric recess. The resulting cylindrical stack capacitor structures are substantially free of defects from rugged polysilicon remaining in the peripheral region thereby improving device yield and process window.

Abstract: The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding. Interfacial oxide layers of order of about 2 to about 3 nm are dissolved away by high temperature annealing, for example, an anneal at 1300°-1330° C. for 1-5 hours. The inventive method is used to best advantage when the Si surfaces at the bonded interface have different surface orientations, for example, when a Si surface having a (100) orientation is bonded to a Si surface having a (110) orientation. In a more general aspect of the invention, the similar annealing processes may be used to remove undesired material disposed at a bonded interface of two silicon-containing semiconductor materials.

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

Abstract: A depletion-type NAND flash memory includes a NAND string composed of a plurality of serially connected FETs, a control circuit which controls gate potentials of the plurality of FETs in a read operation, a particular potential storage, and an adjacent memory cell threshold storage, wherein each of the plurality of FETs is a transistor whose threshold changes in accordance with a charge quantity in a charge accumulation layer, the adjacent memory cell threshold storage stores a threshold of a source line side FET adjacent to a source line side of a selected FET, and the control circuit applies a potential to the gate electrode of the source line side FET in the read operation, the applied potential being obtained by adding a particular potential stored in the particular potential storage to a threshold stored in the adjacent memory cell threshold storage.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: A method for producing a single crystal silicon solar cell including the steps of: implanting ions into a single crystal silicon substrate through an ion implanting surface thereof; closely contacting the single crystal silicon substrate and a transparent insulator substrate with each other via a transparent electroconductive adhesive while using the ion implanting surface as a bonding surface; curing and maturing the transparent electroconductive adhesive into a transparent electroconductive film; applying an impact to the ion implanted layer to mechanically delaminate the single crystal silicon substrate to leave a single crystal silicon layer; and forming a p-n junction in the single crystal silicon layer.

Abstract: A method of manufacturing a semiconductor device, comprises: forming a high dielectric gate insulating film in an nMIS formation region and a pMIS formation region of a semiconductor substrate; forming a first metal film on the high dielectric gate insulating film, the first metal film; removing the first metal film in the nMIS formation region; forming a second metal film on the high dielectric gate insulating film of the nMIS formation region and on the first metal film of the pMIS formation region; and processing the first metal film and the second metal film. The high dielectric gate insulating film has a dielectric constant higher than a dielectric constant of silicon oxide. The first metal film does not contain silicon and germanium. The second metal film contains at least one of silicon and germanium.

Abstract: A method of fabricating a light emitting diode includes the following steps. A substrate is provided and a first semiconductor layer, an active layer, and a second semiconductor layer are placed on the substrate. A carbon nanotube structure is provided and the carbon nanotube structure is lie on the second semiconductor layer. A first electrode is formed on the carbon nanotube structure. A portion of the first semiconductor layer is exposed and a second electrode is formed on the exposed portion of the first semiconductor layer to obtain the light emitting diode.

Abstract: A method for producing a single crystal silicon solar cell including the steps of: implanting ions into a single crystal silicon substrate through an ion implanting surface thereof to form an ion implanted layer in the single crystal silicon substrate; forming a transparent electroconductive film on a surface of a transparent insulator substrate; conducting a surface activating treatment for the ion implanting surface of the single crystal silicon substrate and/or a surface of the transparent electroconductive film on the transparent insulator substrate; bonding the ion implanting surface of the single crystal silicon substrate and the surface of the transparent electroconductive film on the transparent insulator substrate to each other; applying an impact to the ion implanted layer; and forming a p-n junction in the single crystal silicon layer.

Abstract: A backside illuminated image sensor includes a sensor layer comprising photosensitive elements of the pixel array, an epitaxial layer formed on a frontside surface of the sensor layer, and a color filter array formed on a backside surface of the sensor layer. The epitaxial layer comprises polysilicon color filter array alignment marks formed in locations corresponding to respective color filter array alignment mark openings in the frontside surface of the sensor layer. The color filter array is aligned to the color filter array alignment marks of the epitaxial layer. The image sensor may be implemented in a digital camera or other type of digital imaging device.

Abstract: A method of forming a flash memory device in a memory cell region of a substrate includes forming a first insulating layer on the substrate, forming a first conductive layer on the first insulating layer, forming trench isolation regions in the substrate extending through the first conductive layer and the first insulating layer to define an active region in the memory cell region between the trench isolation regions, and selectively removing the first conductive layer and the first insulating layer from the memory cell region of the substrate to expose a surface of the active region between the trench isolation regions.

Abstract: A heat-dissipating semiconductor package structure and a method for manufacturing the same is disclosed. The method includes: disposing on and electrically connecting to a chip carrier at least a semiconductor chip and a package unit; disposing on the top surface of the package unit a heat-dissipating element having a flat portion and a supporting portion via the flat portion; receiving the package unit and semiconductor chip in a receiving space formed by the flat portion and supporting portion of the heat-dissipating element; and forming on the chip carrier encapsulant for encapsulating the package unit, semiconductor chip, and heat-dissipating element. The heat-dissipating element dissipates heat generated by the package unit, provides EMI shielding, prevents delamination between the package unit and the encapsulant, decreases thermal resistance, and prevents cracking.

Abstract: The present invention generally provides apparatus and method for forming a clean and damage free surface on a semiconductor substrate. One embodiment of the present invention provides a system that contains a cleaning chamber that is adapted to expose a surface of substrate to a plasma cleaning process prior to forming an epitaxial layer thereon. In one embodiment, a method is employed to reduce the contamination of a substrate processed in the cleaning chamber by depositing a gettering material on the inner surfaces of the cleaning chamber prior to performing a cleaning process on a substrate. In one embodiment, oxidation and etching steps are repeatedly performed on a substrate in the cleaning chamber to expose or create a clean surface on a substrate that can then have an epitaxial placed thereon. In one embodiment, a low energy plasma is used during the cleaning step.

Abstract: A method for is disclosed for fabricating diluted magnetic semiconductor (DMS) nanowires by providing a catalyst-coated substrate and subjecting at least a portion of the substrate to a semiconductor, and dopant via chloride-based vapor transport to synthesize the nanowires. Using this novel chloride-based chemical vapor transport process, single crystalline diluted magnetic semiconductor nanowires Ga1-xMnxN (x=0.07) were synthesized. The nanowires, which have diameters of ˜10 nm to 100 nm and lengths of up to tens of micrometers, show ferromagnetism with Curie temperature above room temperature, and magnetoresistance up to 250 Kelvin.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.