Abstract: A processing device in a memory sub-system presents a plurality of physical functions to a host system over a physical host interface, the host system to assign the plurality of physical functions to a plurality of tenants executed by the host system, associates a plurality of placement identifiers with the plurality of physical functions, and stores data received from the plurality of tenants in respective segments of a memory device, wherein the respective segments are identified using the plurality of placement identifiers.

Abstract: An electronic device with data processing includes one or more processors configured to in response to receiving a checkpoint signal, determine a location of related data of an application in a memory region, based on the location of the related data in the memory region, perform a checkpointing operation on the related data using either one or both of a host processor and an accelerator processor, and compress the related data using the either one or both of the host processor and the accelerator processor that has performed the checkpointing operation, wherein the location of the related data in the memory region comprises a location in either one or both of a host memory region and an accelerator memory region.

Abstract: A computing system is operable to decode a plurality of incoming streams of digitally encoded data packets to extract a plurality of sets of input data from the plurality of incoming streams of digitally encoded data. A plurality of encrypted user data is generated based on encrypting at least some of the plurality of sets of input data and each of the plurality of encrypted user data is stored via a plurality of different storage locations. The plurality of sets of input data are processed generate a plurality of automatically generated textual data. A plurality of further outgoing streams of digitally encoded data packets are generated and transmitted via processing the plurality of automatically generated textual data.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller is connectable to a host, and is configured to control the nonvolatile memory. The controller is configured to write data to the nonvolatile memory using a plurality of write types with different data write speeds based on information provided by the host, and determine a write ratio of the plurality of the write types.

Abstract: A computer program product, system, and computer implemented method for an approach to provide for efficient on demand block generation for sparseness aware file system. The approaches are discussed in the context of a cluster the uses a distributed storage arrangement that manages objects using entries for snapshots and clones that are managed together. Specifically, the present disclosure provides for an approach where metadata for snapshots and clones of the object (e.g., extent) can be managed using a single set of metadata that intermingles entries for any number of snapshots and clones of the object (or subsets thereof) together. This is further combined with support for variable sized allocation units and tombstones (that represent sparse data using metadata), where those tombstones corresponding to data that can be generated on demand using application or file specific context generation logic to improve storage efficiency and reduce storage requirements.

Abstract: A first series of memory access transactions are received from a first set of compressed data having a number of first transactions indeterminate in a transaction receiver, and a second series of memory access transactions are received from a second set of compressed data having a number of second transactions indeterminate in the transaction receiver. A count of outstanding transactions for the combined first and second sets of compressed data is received in the transaction receiver, and memory space is allocated for the first and second series of transactions based at least in part on the received count of outstanding combined transactions. The first series of transactions are stored sequentially from a first end of the allocated memory space and the second series of transactions are stored sequentially from a second end of the allocated memory space opposite the first end.

Abstract: An operating system, or operating system update, management service uses a shared read-only multi-attach volume of a block-based storage service to distribute operating systems or operating system updates to a set of virtualized computing instances. Also, to store launch specific information, that is specific to a given virtualized computing instance, additional writable volumes are used, wherein a write volume is attached to each of the computing instances of the set. This eliminates the need to provide a full copy of an OS volume to each of the computing instances.

Abstract: One or more example embodiments are directed to a storing method of an embedding table, an apparatus, an electronic device, a non-transitory storage medium, and/or a system, the storing method including: acquiring an embedding table; and storing the embedding table in a memory of at least one CXL-PNM device, the storing enabling the at least one CXL-PNM device to perform parallel lookup of the embedding table in the memory using processing circuitry of the at least one CXL-PNM device, wherein the at least one CXL-PNM device includes the memory and the processing circuitry.

Abstract: A method and device are provided in which a request is received at a cache memory. The request includes a first tag, and the first tag includes bits. A first comparison is performed of a first subset of the bits to entries of a first storage of the cache memory. Each entry of the first storage comprises a subset of bits of a corresponding tag in a second storage of the cache memory. One or more potential matching entries of the second storage for the request are determined based on the first comparison. In response to the determining the one or more potential matching entries, a second comparison is performed of the bits to tags of the one or more potential matching entries to determine whether the second storage comprises a matching entry for the request.

Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. The computing devices may use local caches in a coherent manner when accessing the plurality of storage devices.

Abstract: Techniques for maintaining cache coherency while sharing data among multiple processors are disclosed. Multiple coherent elements are arranged in an M×N mesh topology. An element can include a compute coherency block (CCB), and a coherency ordering agent (COA). The COAs include a directory snoop filter (DSF), an eviction content addressable memory (eCAM), a miss and snoop queue (MSQ), and a pipeline logic. The CCB and COA include functions for interfacing with a hierarchical cache and directory snoop filter (DSF). A CCB from within one of the multiple coherent elements issues a read request. The corresponding directory snoop filter (DSF) is inspected to determine if there is a slot (way) available for storing information pertaining to the read request. In the event that no eligible vacancies are present in the DSF, a multi-pass process for handling a capacity limit in a DSF is performed.

Abstract: A packet processing device, a method to be performed at the packet processing device, a computer-readable storage medium, and a computing system. The packet processing device is to determine a computing unit of the server architecture, the computing unit to execute a workload; receive a data packet including data to be used by the computing unit to execute the workload; determine, based on the computing unit to execute the workload, a memory of the server architecture to store the data for access by the computing unit to execute the workload; and route the data to the server architecture for storage at the memory.

Abstract: A computer-implemented method includes calculating a respective availability score for each of a plurality of backup computing action processing channels based on respective responses of the plurality of backup computing action processing channels to one or more of a plurality of test computing actions or a plurality of historical computing actions, receiving a requested computing action from a user, determining that a primary computing action processing channel cannot successfully process the requested computing action within one or more of a reliability threshold or a latency threshold, in response to determining that the primary computing action processing channel cannot successfully process the requested computing action, selecting a backup computing action processing channel from the plurality of backup computing action processing channels according to the availability scores, and transmitting the requested computing action to the selected backup computing action processing channel.

Abstract: An authentication server capable of accessing data in a memory of a control device is configured to: detect authentication input information being written into the memory by monitoring access to the memory and read, from the memory, the authentication input information written into the memory; check the authentication input information against account information registered in a user database to generate an authentication result for the authentication input information; and write the authentication result for the authentication input information into the memory of the control device, thereby to notify the control device of availability of control processing based on the authentication result.

Abstract: Discussed herein are devices, systems, machine-readable media, and methods for reduced pin count stackable memory. A stackable memory device includes a first surface with a set of input pins, the set of input pins configured to receive chip select signals from an address decoder of a controller; a second surface with a set of output pins, the set of output pins arranged in a similar configuration to the set of input pins to enable coupling and stacking of multiple stackable memory devices; and a cascade routing signal scheme including: a set of dedicated point-to-point signal paths configured to shift the chip select signals from the set of input pins by one but when propagated to the set of output pins; and an enable point-to-point signal path configured to connect a first input pin to an enable component of the stackable memory device.

Abstract: Embodiments herein describe a configurable engine that is embedded into the cache hierarchy of a processor. The configurable engine can enable efficient data sharing between the main memory, cache memories, and the core. The configurable engine can perform operations that are more efficient to be done in the cache hierarchy. In one embodiment, the configurable engine is controlled (or configured) by software (e.g., the operating system (OS)), adapting to each application domain. That is, the OS can configure the engine according to a data flow profile of a particular application being executed by the processor.

Abstract: Modulation of the source voltage in a NAND-flash array read waveform can enable improved read-disturb mitigation. For example, increasing the source line voltage to a voltage with a magnitude greater than the non-idle source voltage during the read operation when the array is idle (e.g., not during sensing) enables a reduction in read disturb without the complexity arising from the consideration of multiple read types. Additional improvement in FN disturb may also be obtained on the sub-blocks in the selected SGS by increasing the source line voltage during the selected wordline ramp when the array is idle.

Abstract: The present application provides a processor and a method for memory access instruction, and an electronic device, and relates to the field of computer technology. The method includes: the memory access unit generates the target physical memory address corresponding to the memory access instruction in case of receiving the memory access instruction, and transmits the target physical memory address to the cache unit and the programmable physical memory property detection unit respectively in the current clock cycle; the programmable physical memory property detection unit determines the detection result for the cache property of the target physical memory address in the current clock cycle; the cache unit performs the memory access operation at the target physical memory address based on the detection result for the cache property in the next clock cycle subsequent to the current clock cycle. This may reduce the logical depth of the critical memory access paths and improve the clock speed of the processor.

Abstract: In accordance with the described techniques, a processor includes a cache system having a level two cache, and a hardware prefetcher associated with the level two cache. The hardware prefetcher monitors a workload that includes accesses to the level two cache, and measures a degree of thrashing exhibited by the workload in the level two cache based on the accesses. Prefetch requests issued by the hardware prefetcher are throttled based on the degree of thrashing being greater than or equal to a thrashing threshold.

Abstract: A method includes receiving, by a level two (L2) controller, a write request for an address that is not allocated as a cache line in a L2 cache. The write request specifies write data. The method also includes generating, by the L2 controller, a read request for the address; reserving, by the L2 controller, an entry in a register file for read data returned in response to the read request; updating, by the L2 controller, a data field of the entry with the write data; updating, by the L2 controller, an enable field of the entry associated with the write data; and receiving, by the L2 controller, the read data and merging the read data into the data field of the entry.