Abstract: An authentication server capable of accessing data in a memory of a control device is configured to: detect authentication input information being written into the memory by monitoring access to the memory and read, from the memory, the authentication input information written into the memory; check the authentication input information against account information registered in a user database to generate an authentication result for the authentication input information; and write the authentication result for the authentication input information into the memory of the control device, thereby to notify the control device of availability of control processing based on the authentication result.

Abstract: Discussed herein are devices, systems, machine-readable media, and methods for reduced pin count stackable memory. A stackable memory device includes a first surface with a set of input pins, the set of input pins configured to receive chip select signals from an address decoder of a controller; a second surface with a set of output pins, the set of output pins arranged in a similar configuration to the set of input pins to enable coupling and stacking of multiple stackable memory devices; and a cascade routing signal scheme including: a set of dedicated point-to-point signal paths configured to shift the chip select signals from the set of input pins by one but when propagated to the set of output pins; and an enable point-to-point signal path configured to connect a first input pin to an enable component of the stackable memory device.

Abstract: Modulation of the source voltage in a NAND-flash array read waveform can enable improved read-disturb mitigation. For example, increasing the source line voltage to a voltage with a magnitude greater than the non-idle source voltage during the read operation when the array is idle (e.g., not during sensing) enables a reduction in read disturb without the complexity arising from the consideration of multiple read types. Additional improvement in FN disturb may also be obtained on the sub-blocks in the selected SGS by increasing the source line voltage during the selected wordline ramp when the array is idle.

Abstract: Embodiments herein describe a configurable engine that is embedded into the cache hierarchy of a processor. The configurable engine can enable efficient data sharing between the main memory, cache memories, and the core. The configurable engine can perform operations that are more efficient to be done in the cache hierarchy. In one embodiment, the configurable engine is controlled (or configured) by software (e.g., the operating system (OS)), adapting to each application domain. That is, the OS can configure the engine according to a data flow profile of a particular application being executed by the processor.

Abstract: The present application provides a processor and a method for memory access instruction, and an electronic device, and relates to the field of computer technology. The method includes: the memory access unit generates the target physical memory address corresponding to the memory access instruction in case of receiving the memory access instruction, and transmits the target physical memory address to the cache unit and the programmable physical memory property detection unit respectively in the current clock cycle; the programmable physical memory property detection unit determines the detection result for the cache property of the target physical memory address in the current clock cycle; the cache unit performs the memory access operation at the target physical memory address based on the detection result for the cache property in the next clock cycle subsequent to the current clock cycle. This may reduce the logical depth of the critical memory access paths and improve the clock speed of the processor.

Abstract: In accordance with the described techniques, a processor includes a cache system having a level two cache, and a hardware prefetcher associated with the level two cache. The hardware prefetcher monitors a workload that includes accesses to the level two cache, and measures a degree of thrashing exhibited by the workload in the level two cache based on the accesses. Prefetch requests issued by the hardware prefetcher are throttled based on the degree of thrashing being greater than or equal to a thrashing threshold.

Abstract: A method includes receiving, by a level two (L2) controller, a write request for an address that is not allocated as a cache line in a L2 cache. The write request specifies write data. The method also includes generating, by the L2 controller, a read request for the address; reserving, by the L2 controller, an entry in a register file for read data returned in response to the read request; updating, by the L2 controller, a data field of the entry with the write data; updating, by the L2 controller, an enable field of the entry associated with the write data; and receiving, by the L2 controller, the read data and merging the read data into the data field of the entry.

Abstract: Provided are systems, methods, and apparatuses for assisted cache data placement. In one or more examples, systems, methods, and apparatuses include assigning a first identifier to first data based on an aspect of the first data, the first data being data moved from a cache and assigning a second identifier to second data based on an aspect of the second data, the second data being moved to a storage device based on a policy of the cache. In one or more examples, systems, methods, and apparatuses include storing the first data in a first storage location of the storage device based on the first identifier and storing the second data in a second storage location of the storage device based on the second identifier.

Abstract: Disclosed are various embodiments for garbage collection for object-based storage systems. A first set of objects stored in a data object store is identified as not meeting criteria for deletion or archiving, the criteria specified in a retention policy. A second set of objects is identified by performing a search of the object data store for data objects belonging to a data structure with the first set of objects. The second set of objects is recorded as not meeting the criteria for deletion or archiving. The second set of data objects are retained, based on the recording, to prevent the data structure from being corrupted.

Abstract: A method for managing data packing in a storage includes: receiving data from a computing device at a first point-in-time; analyzing the data to: determine characteristics of the data, and generate an extent for the data, in which the extent includes sequential tracks; analyzing sequential tracks to infer how a distribution of compression sizes change for the sequential tracks to obtain track-level in the compression sizes; forecasting, based on the characteristics of the data and the track-level changes in the compression sizes, a stability score of the distribution at a second point-in-time, in which the second point-in-time is after the first point-in-time; making a determination, based on the stability score, that the distribution would be the same in the second point-in-time; and placing, based on the determination, the tracks to a first zone in the storage, in which the storage further comprises a second zone and a third zone.

Abstract: A method of processing transactions associated with a command in a storage system is provided. The method includes receiving, at a first authority of the storage system, a command relating to user data. The method includes sending a transaction of the command, from the first authority to a second authority of the storage system, wherein a token accompanies the transaction and writing data in accordance with the transaction as permitted by the token into a partition that is allocated to the second authority in a storage device of the storage system.

Abstract: A solver system may employ a cache. A cache component may be configured accept inputs and send outputs in the same manner and/or using the same protocols as a solver component. A central manager component may receive a problem from a requestor, and send the problem to one or more solver components and a cache component. If the cache component identifies a stored result, it may return it to the manager component, and the manager component may send the result to the requestor. If the cache component does not identify a stored result (or otherwise does not respond to the manager component), the solver component(s) may operate normally to determine a result and return it to the manager component. In this architecture, however, the cache component is outside of the critical path, and thus the cache search does not increase the latency of the response.

Abstract: An electronic device includes a processor, the processor having a cache memory, a set of physical registers, and a promotion logic functional block. When one or more promotion conditions are met, the promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory to a physical register among the set of physical registers. For promoting the prefetched data, the promotion logic functional block acquires the prefetched data from the portion of the cache block and stores the prefetched data in the physical register.

Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink. The passive crosslink is a passive interposer die dedicated for inter-chiplet communications and partitions systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

Abstract: Aspects of the disclosure are directed to providing access to multimedia data in a tile format. In accordance with one aspect, the disclosure includes detecting one or more dependencies of a first tile read request with a second tile read request by classifying a head node and a dependent node; sending the first tile read request to a main memory; storing the dependent node in a buffer; and outputting a first cache line and a second cache line using the first tile read request.

Abstract: A multi-port memory device in communication with a controller includes a memory array for storing data provided by the controller, a first port coupled to the controller via a first controller channel, a second port coupled to the controller via a second controller channel, a processor, and a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to: enable data transfer through the first port and/or the second port in response to a first control signal received from the first controller channel and/or a second control signal received from second controller channel, decode at least one of the received first and second control signals to identify a data operation to perform, the identified data operation including a read or write operation from or to the memory array, and execute the identified data operation.

Abstract: A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.

Abstract: Partial address memory requests for data are described. In accordance with the described techniques, an accelerator receives a request for data that does not include address information for a data storage location from which the data is to be retrieved. The accelerator identifies at least one data storage location that includes data produced by the accelerator and retrieves the data from the at least one data storage location. A result is then output by the accelerator that includes the data retrieved from the at least one data storage location.

Abstract: A method of operating a memory system is provided. A logical-to-physical (L2P) address mapping table is obtained in response to a data request instruction. Corresponding data is read from a memory device based on the L2P address mapping table. The L2P address mapping table includes a base physical address of continuous first physical addresses corresponding to first logic addresses and a base physical address offset corresponding to the continuous first physical addresses.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows and a row hammer management circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row. The row hammer management circuit includes a hammer address queue. The row hammer management circuit changes the updated count data randomly, based on an event signal indicating a state change of the hammer address queue.