Patents Examined by Jae U Yu
  • Patent number: 12293113
    Abstract: A method for storing and reading cached data and a device are provided. The method for storing and reading cached data includes: in response to receiving to-be-cached data, segmenting the to-be-cached data sequentially into at least two pieces of first fragmented data; writing the first fragmented data sequentially into first storage particles of at least two storage blocks in a time division multiplexing manner, and ensuring that the first fragmented data written into the respective first storage particles are different from each other. The fragmented data are stored and read in the time division multiplexing manner, and the fragmented data corresponding to a complete data are stored in different storage blocks, so a plurality of data can be stored and read in a complete data storage and read process, thereby reducing read and write time overhead during the execution of a large number of buffered data storage and read tasks.
    Type: Grant
    Filed: February 22, 2024
    Date of Patent: May 6, 2025
    Assignee: YUSUR Technology Co., Ltd.
    Inventors: Jian Jin, Shuanglin Zhang
  • Patent number: 12287729
    Abstract: A processing device comprises processors, a first memory shared by the processors, and a cache comprising a second memory comprising a plurality of memory units, each of the plurality of memory units in the second memory being associated with a respective one of a plurality of request identifiers. The cache receives a memory read request including a request identifier and a memory address from at least one of the processors, identifies an allocated memory address identifier for the memory address, accesses the first memory to read data of the memory address, obtains one or more request identifiers which requested data of the memory address from the second memory based on the allocated memory address identifier, and transmitting the data of the memory address to one or more processors which requested data of the memory address based on the one or more request identifiers.
    Type: Grant
    Filed: March 7, 2024
    Date of Patent: April 29, 2025
    Assignee: Rebellions Inc.
    Inventors: Sungpill Choi, Jae-Sung Yoon
  • Patent number: 12277062
    Abstract: In asynchronous remote replication, write IOs are accumulated in capture cycles and sent to a remote storage system in transmit cycles. In order to cause metadata cache hits at the remote storage system, write IO data and associated metadata hints such as logical block addresses being updated are sent in successive cycles. The metadata hints, which are received at the remote storage system before the corresponding write IO data, are used to prefetch metadata associated with the logical block addresses being updated to replicate the write IO.
    Type: Grant
    Filed: December 7, 2023
    Date of Patent: April 15, 2025
    Assignee: Dell Products L.P.
    Inventors: Sandeep Chandrashekhara, Ramesh Doddaiah, Mohammed Asher, Aamir Mohammed
  • Patent number: 12277059
    Abstract: The present application discloses a method and apparatus for reducing a mirror data transmission amount by a dual layer cache, and a device and a medium. The method includes: after receiving an input/output (IO) request, writing, by a first node, the IO request into a first upper-layer cache space; writing, by the first node, first cached data corresponding to the IO request into a first lower-layer cache space according to the IO request, and generating, by the first node, first index information for the first cached data; writing mirror data of the IO request into a second upper-layer cache space of a second node; and writing mirror data of the first index information into a second lower-layer cache space of the second node.
    Type: Grant
    Filed: December 20, 2024
    Date of Patent: April 15, 2025
    Assignee: Suzhou MetaBrain Intelligent Technology Co., Ltd.
    Inventors: Xiangfei Kong, Yonggang Wang
  • Patent number: 12271588
    Abstract: The disclosed device includes a memory-semantic fabric comprising memory components accessible by multiple processors and a controller for the memory-semantic fabric. The controller receives, from multiple processes, memory requests for a memory-semantic fabric. The controller also identifies, within the processes, a source process for each of the memory requests and prioritizes forwarding the memory requests to the memory-semantic fabric based on the source processes. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: April 8, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Atul Kumar Sujayendra Sandur, Sergey Blagodurov, Nathaniel Morris
  • Patent number: 12271309
    Abstract: Systems and techniques are disclosed for relative age tracking for entries in a buffer. For example, some techniques may include pre-computing age matrix entries of an age matrix corresponding to invalid entries of a data buffer based on a validity indication (e.g., a valid bit mask), wherein the validity indication identifies valid entries in the data buffer and the age matrix tracks relative ages of the entries in the data buffer; responsive to data being received for storage in the data buffer, selecting an entry corresponding to an index value in the data buffer from among a set of invalid entries of the data buffer; storing the data in the entry corresponding to the index value; and updating the validity indication to indicate that the entry corresponding to the index value is valid.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: April 8, 2025
    Assignee: SiFive, Inc.
    Inventor: Wesley Waylon Terpstra
  • Patent number: 12260127
    Abstract: Techniques for storage and processing for distributed file systems are disclosed. In the illustrative embodiment, padding is placed between data elements in a file to be stored on a distributed file system. The file is to be split into several objects in order to be stored in the distributed file system, and the padding is used to prevent a data element from being split across two different objects. The objects are stored on data nodes, which analyze the objects to determine which data elements are present in the object as well at the location of those objects. The location of the objects is saved on the data storage device, and those locations can be used to perform queries on the data elements in the object on the data storage device itself. Such an approach can reduce transfer of data elements from data storage to local memory of the data node.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: March 25, 2025
    Assignee: Intel Corporation
    Inventors: John S. Keys, Daniel R. McLeran, Ian F. Adams, Michael P. Mesnier, Nilesh N. Shah
  • Patent number: 12259788
    Abstract: Techniques for UNDO and REDO operations in a computer-user interface are disclosed. The techniques enables users to configure entities for UNDO and REDO operations. The techniques also enable users to roll back individual entity to an immediate previous state in one UNDO operation and subsequently to the other previous states. Other entities are not affected by the UNDO operations to the entity.
    Type: Grant
    Filed: May 2, 2024
    Date of Patent: March 25, 2025
    Assignee: Oracle International Corporation
    Inventors: Satish Chandra Oruganti, Ganesh Kumar Gupta, Michael Patrick Rodgers
  • Patent number: 12248710
    Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. The computing devices may use local caches in a coherent manner when accessing the plurality of storage devices.
    Type: Grant
    Filed: March 8, 2024
    Date of Patent: March 11, 2025
    Assignee: Weka.IO Ltd.
    Inventors: Maor Ben Dayan, Omri Palmon, Liran Zvibel, Kanael Arditti, Artemy Voikhansky, Alex Goltman
  • Patent number: 12235763
    Abstract: The present disclosure provides a data processing method, a device, a computer apparatus and a storage medium, wherein the method includes: in response to a target disk receiving at least one write request within a preset time period, determining a size threshold value for classifying a data update type according to a size of write data respectively indicated by each write request; determining a data update type corresponding to each write request according to a size of each write request and the size threshold value; dividing write data of the write request to obtain a data block according to a preset data block size, and caching the data block in a cache region of the target disk corresponding to the data update type, the target disk has multiple types of cache regions configured therein, different cache regions are configured to support caching of data with different update frequencies.
    Type: Grant
    Filed: June 13, 2024
    Date of Patent: February 25, 2025
    Assignees: Xi'an Jiaotong University, Douyin Vision Co., Ltd., Lemon Inc.
    Inventors: Wei Tang, Chi Zhang, Fangxing Yu, Menghan Li, Bo Wang, Weiguo Wu, Fei Liu
  • Patent number: 12235762
    Abstract: Disclosed are a data access method and apparatus, a device, and a computer-readable storage medium, the method including: creating a cache pool matching memory capacity of an accelerator card on a host side, the cache pool containing cache blocks divided according to a set capacity unit; under a condition that acquiring a read instruction of target data, calling from the cache pool a target cache block matching capacity of the target data; storing the target data into the target cache block, recording meta information about the target cache block, and setting write protection for the target cache block; and executing a data access operation according to state information corresponding to the cache blocks, and adjusting the state information about the cache blocks after executing the data access operation.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: February 25, 2025
    Assignee: IEIT SYSTEMS CO., LTD.
    Inventor: Ke Liu
  • Patent number: 12235760
    Abstract: Apparatus might include a first plurality of signal lines, a second plurality of signal lines, a controller, a first die, and a second die. The controller, the first die, and the second die might each be connected to the first plurality of signal lines and connected to the second plurality of signal lines. The first die and the second die might each include termination circuitry connected to a particular signal line of the second plurality of signal lines. The first die might be configured to activate its termination circuitry in response to receiving a particular combination of signal values on the first plurality of signal lines. The second die might be configured to deactivate its termination circuitry in response to receiving the particular combination of signal values on the first plurality of signal lines.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: February 25, 2025
    Assignee: Lodestar Licensing Group LLC
    Inventor: Terry Grunzke
  • Patent number: 12236997
    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: February 25, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kiheung Kim, Taeyoung Oh, Jongcheol Kim, Kyungho Lee, Hyongryol Hwang
  • Patent number: 12223191
    Abstract: An operating system, or operating system update, management service uses a shared read-only multi-attach volume of a block-based storage service to distribute operating systems or operating system updates to a set of virtualized computing instances. Also, to store launch specific information, that is specific to a given virtualized computing instance, additional writable volumes are used, wherein a write volume is attached to each of the computing instances of the set. This eliminates the need to provide a full copy of an OS volume to each of the computing instances.
    Type: Grant
    Filed: September 29, 2023
    Date of Patent: February 11, 2025
    Assignee: Amazon Technologies, Inc.
    Inventor: Amit Shah
  • Patent number: 12222864
    Abstract: Data can be rapidly and flexibly converted. A data conversion apparatus stores monitoring target management information in which a monitoring target is associated with a controller type representing a type of a controller configured to control the monitoring target, and data conversion rule information in which a data set in units of the controller type is registered, the data set in units of the controller type defining a conversion rule indicating a data conversion method for the controller type. A calculation unit loads the data conversion rule information into the cache memory, specifies a monitoring target corresponding to data received from an edge device, specifies a controller type corresponding to the specified monitoring target by referring to the monitoring target management information, reads a conversion rule corresponding to the specified controller type from the cache memory, and converts the data using the conversion rule.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: February 11, 2025
    Assignee: HITACHI, LTD.
    Inventors: Naushad Shakoor, Koichi Okita, Yuta Sekiguchi
  • Patent number: 12216945
    Abstract: A direct-attached storage device software RAID hibernation system includes a chassis having an operating system, a bus driver subsystem, controller devices coupled to physical storage devices, and a software RAID subsystem coupled to the operating system and the controller devices. While in a runtime mode, the software RAID subsystem presents the operating system a primary controller device as being connected to a logical storage device provided by the physical storage devices, and provides a filter subsystem in a secondary controller device that controls at least one of the physical storage devices. While in the runtime mode, the filter subsystem identifies a controller initialization request from the operating system that requests initialization of the secondary controller device and, in response, transmits a power-down prevention communication to the bus driver subsystem that is configured to prevent the bus driver subsystem from powering down the secondary controller device during a hibernation mode.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: February 4, 2025
    Assignee: Dell Products L.P.
    Inventors: Abhijit Shashikant Mirajkar, Abhijit Rajkumar Khande, Nikhith Ganigarakoppal Kantharaju, Ajay Sukumaran Nair Syamala Bai
  • Patent number: 12204469
    Abstract: A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.
    Type: Grant
    Filed: February 26, 2024
    Date of Patent: January 21, 2025
    Assignee: Rambus Inc.
    Inventors: Hongzhong Zheng, Brent Haukness
  • Patent number: 12197345
    Abstract: A data processing method and a storage apparatus are disclosed. The data processing method includes: receiving, by an NVMe storage device, an NVMe write command sent by a host, where the NVMe write command carries a key and a value pointer, the value pointer points to first storage space, and the first storage space is used to store a value; obtaining, by the NVMe storage device, the key from the NVMe write command and a value length, and allocating second storage space to the value according to the value length, where the second storage space is in the NVMe storage device; and obtaining, by the NVMe storage device, the value from the host, and storing the value in the second storage space.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: January 14, 2025
    Assignee: Huawei Technologies Co., Ltd
    Inventors: Xin Qiu, Huifeng Xu, Haitao Guo, Hongguang Liu, Huawei Liu, Chunyi Tan, Victor Gissin
  • Patent number: 12189530
    Abstract: Disclosed is a system and method for use in a cache for suppressing modification of cache line. The system and method includes a processor and a memory operating cooperatively with a cache controller. The memory includes a coherence directory stored within a cache created to track at least one cache line in the cache via the cache controller. The processor instructs a cache controller to store a first data in a cache line in the cache. The cache controller tags the cache line based on the first data. The processor instructs the cache controller to store a second data in the cache line in the cache causing eviction of the first data from the cache line. The processor compares based on the tagging the first data and the second data and suppresses modification of the cache line based on the comparing of the first data and the second data.
    Type: Grant
    Filed: March 29, 2024
    Date of Patent: January 7, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Paul J. Moyer
  • Patent number: 12189531
    Abstract: The present disclosure provides a data processing method, a device, a computer apparatus and a storage medium, wherein the method includes: in response to a target disk receiving at least one write request within a preset time period, determining a size threshold value for classifying a data update type according to a size of write data respectively indicated by each write request; determining a data update type corresponding to each write request according to a size of each write request and the size threshold value; dividing write data of the write request to obtain a data block according to a preset data block size, and caching the data block in a cache region of the target disk corresponding to the data update type, the target disk has multiple types of cache regions configured therein, different cache regions are configured to support caching of data with different update frequencies.
    Type: Grant
    Filed: June 13, 2024
    Date of Patent: January 7, 2025
    Assignees: Xi'an Jiaotong University, Douyin Vision Co., Ltd., Lemon Inc.
    Inventors: Wei Tang, Chi Zhang, Fangxing Yu, Menghan Li, Bo Wang, Weiguo Wu, Fei Liu