Patents Examined by Jae U Yu
  • Patent number: 10353614
    Abstract: A RAID system and method based on a solid-state storage medium. The system includes a plurality of solid-state storage devices and a main control unit. Each solid-state storage device includes a solid-state storage medium and a controller for controlling reading and writing of the solid-state storage medium. The main control unit is electrically connected to the controller of each of the solid-state storage devices in a RAID array. The main control unit is used for performing address mapping from a logical block address in the RAID array to a physical block address of the flash memory solid-state storage device. The address mapping and the RAID function can be integrated to solve the problems of write amplification and low performance. The unified management of address mapping of the solid-state storage devices can be implemented to improve the efficiency of garbage collection and wear leveling of the solid-state storage system.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: July 16, 2019
    Assignee: SHANNON SYSTEMS LTD.
    Inventor: Xueshi Yang
  • Patent number: 10346227
    Abstract: Techniques described herein generally include methods and systems related to designing and operating a DRAM device that has significantly reduced refresh energy use. A method for designing a DRAM optimizes or otherwise improves the DRAM for energy efficiency based on a measured or predicted failure probability of memory cells in the DRAM. The DRAM may be configured to operate at an increased refresh interval, thereby reducing DRAM refresh energy but causing a predictable portion of the memory cells in the DRAM to leak electrical energy too quickly to retain data. The DRAM is further configured with a selected number of spare memory cells for replacing the “leaky” memory cells, so that operation of the DRAM at the increased refresh interval may result in little or no reduction in capacity of the DRAM.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: July 9, 2019
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 10338852
    Abstract: Systems and methods for list retrieval in a storage device are provided that significantly reduces the number of commands needed to retrieve data. A single command or request may be issued to receive data stored at a parent node, a child node, and/or a grandchild node. For example, a request may be issued that includes a node corresponding to a particular level, a depth level below that particular level to which to obtain data and/or filter criteria. With this information, the requested information may be obtained to the depth level while filtering out information not included in the request. When the request corresponds to a parent node and information about the children nodes is desired, for example, additional requests are not needed to obtain information from all of the parent node and the children nodes. Thus, the length of time needed to provide certain stored management information is reduced.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: July 2, 2019
    Assignee: Oracle International Corporation
    Inventors: Archana Katarki, James Kremer
  • Patent number: 10338843
    Abstract: A method for moving data internally, performed by a processing unit, including at least the following steps. The processing unit transmits partial copyback read commands to a storage sub-unit through an access interface, where each partial copyback read command is used to direct logic circuits of the storage sub-unit to store partial data of a page of the storage sub-unit in a designated location of a data buffer of the storage sub-unit. The processing unit further transmits a copyback write command to the storage sub-unit through the storage sub-unit for programming the data of the data buffer in a new page of the storage sub-unit.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: July 2, 2019
    Assignee: Silicon Motion, Inc.
    Inventors: Hsu-Ping Ou, Chih-Kang Kung
  • Patent number: 10324845
    Abstract: Techniques are provided for automatic placement of cache operations in a dataflow. An exemplary method obtains a graph representation of a dataflow of operations; determines a number of executions and a computational cost of the operations, and a computational cost of a caching operation to cache a dataset generated by an operation; establishes a dataflow state structure recording values for properties of the dataflow operations for a number of variations of caching various dataflow operations; determines a cache gain factor for dataflow operations as an estimated reduction in the accumulated cost of the dataflow by caching an output dataset of a given operation; determines changes in the dataflow state structure by caching an output dataset of a different operation in the dataflow; and searches the dataflow state structures to determine the output datasets to cache based on a total dataflow execution cost.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: June 18, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Vinicius Michel Gottin, Edward José Pacheco Condori, Jonas F. Dias, Angelo E. M. Ciarlini, Bruno Carlos da Cunha Costa, Wagner dos Santos Vieira, Paulo de Figueiredo Pires, Fábio André Machado Porto, Yania Molina Souto
  • Patent number: 10318346
    Abstract: Data stores may implement prioritized scheduling of data store access requests. When new access requests are received, the new access requests may be scheduled for prioritized execution on processing resources. Access requests that are currently being executed with prioritized execution may be reprioritized to make additional capacity for prioritized execution of the new access requests. Prioritized execution may be automatically enabled or disabled for a data store based on monitoring of performance metrics for executing access requests.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: June 11, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Stavros Harizopoulos, Michail Petropoulos, Andrea Olgiati
  • Patent number: 10318382
    Abstract: A method includes determining, by a computing device of a dispersed storage network (DSN), a source name for a data object to be scanned for missing encoded data slices. The method further includes issuing list source requests to the set of storage units. When a list source response is not received from a storage unit of the set of storage units within a response timeframe, the method further includes identifying one or more encoded data slices stored on the storage unit as potentially missing encoded data slices; determining a next level missing encoded data slice determination approach for the storage unit based on one or more of: a number of potentially missing encoded data slices, a performance goal, a network loading level, a rebuilding loading level, a predetermination, and an entry of a system registry; and executing the next level missing encoded data slice determination approach.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Thomas F. Shirley, Jr., Gary W. Grube, Bart R. Cilfone, Ravi V. Khadiwala, Greg R. Dhuse, Thomas D. Cocagne, Michael C. Storm, Yogesh R. Vedpathak, Wesley B. Leggette, Jason K. Resch, Andrew D. Baptist, Ilya Volvovski
  • Patent number: 10318440
    Abstract: An example method for remapping a group of system registers. The method may include receiving, by a secure access control mechanism, a request to remap one of a group of system registers from an association with a first access policy group to an association with a second access policy group. The method may include storing the remapping array at a memory of the secure access control mechanism, where a first value stored in a first entry of the remapping array maps the one of the group of system registers to the second access policy group. The method may include remapping, by the secure access control mechanism, the one of a group of system registers from the association with the first access policy group to the association with the second access policy group using the remapping array.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Nagaraju N. Kodalapura, Vladimir Beker, Raghunandan Makaram
  • Patent number: 10310982
    Abstract: A computer-implemented method for managing cache memory in a distributed symmetric multiprocessing computer is described. The method may include receiving, at a first central processor (CP) chip, a fetch request from a first chip. The method may further include determining via address compare mechanisms on the first CP chip whether one or more of a second CP chip and a third CP chip is requesting access to a target line. The first chip, the second chip, and the third chip are within the same chip cluster. The method further includes providing access to the target line if both of the second CP chip and the third CP chip have accessed the target line at least one time since the first CP chip has accessed the target line.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Deanna Postles Dunn Berger, Johnathon J. Hoste, Pak-kin Mak, Arthur J. O'Neill, Jr., Robert J. Sonnelitter, III
  • Patent number: 10310771
    Abstract: Described embodiments provide systems and methods for operating a storage system. A portion of data currently on a source Logical Unit (LUN) of a disk array of a plurality of disk arrays is written to a destination LUN of a disk array of a plurality of disk arrays. The destination LUN of a disk array of the plurality of disk arrays to write the data to is established based on an efficiency indicator associated with the destination LUN of a disk array of the plurality of disk arrays. The writing at least a portion of data currently on a source LUN of a disk array of a plurality of disk arrays may be performed as part of a replication process or as part of a relocation process.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: June 4, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Felix Shvaiger, Arieh Don, Anton Kucherov
  • Patent number: 10310987
    Abstract: Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss corresponding to a request for a virtual address to physical address translation, searching a cache that includes virtual addresses and page sizes that correspond to translation table entries (TTEs) that have been evicted from the L1TLB, where a page size is identified, and searching a second level TLB and identifying a physical address that is contained in the second level TLB. Access is provided to the identified physical address.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: June 4, 2019
    Assignee: INTEL CORPORATION
    Inventors: Karthikeyan Avudaiyappan, Mohammad Abdallah
  • Patent number: 10296233
    Abstract: A method of managing a message transmission flow and a storage device using the method are provided. The method of managing a message transmission flow includes receiving, at a storage device, response transmission type information in at least one of a command phase and a data phase, and transmitting response information to a host in at least one of a normal mode and a fast mode based on the received response transmission type information. The normal mode and the fast mode have different latencies.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: May 21, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-yeon Kim, Jin-woo Kim
  • Patent number: 10296264
    Abstract: A method of selecting among a plurality of I/O streams through which data is to be written to a multi-streaming flash storage device is presented. According to an example embodiment, the method comprises: assigning write sequences of similar length to the same I/O streams; receiving instructions for a write operation, the instructions including a starting logical block address (LBA) and a number of blocks of data to be written; determining whether the write operation is part of an existing write sequence; identifying an I/O stream associated with an existing write sequence; and providing a stream ID of the identified I/O stream to the multi-streaming flash storage device.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sina Hassani, Anahita Shayesteh, Vijay Balakrishnan
  • Patent number: 10289345
    Abstract: A mapping apparatus comprises a mapper that translates from an input key to an output key in one or more storage devices. A pre-mapper for processing update operations comprises a plurality of mapping tablets and an in-memory look-up filter to identify a given mapping table storing a given input key. The mapping tablets comprise at least one dynamic in-memory ingress tablet and a plurality of persisted frozen tablets. For a given update operation, a first entry is added to one dynamic in-memory ingress tablet comprising the input key for the given update operation and a corresponding output key where data for the given update operation is stored; and a second entry is added to the look-up filter comprising the input key of the first entry and an identifier of the dynamic in-memory ingress tablet storing the first entry for the given update operation. The dynamic in-memory ingress tablet is persisted as a persisted frozen tablet.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 14, 2019
    Assignee: EMC IP Holding Company LLC
    Inventor: Joris Wils
  • Patent number: 10289566
    Abstract: A technique involves, from an incoming flow of data that includes a first stream from a first source and another stream from another source, placing data of the first stream into first storage segments and data of the other stream into other storage segments that are different from the first storage segments. The technique further involves, while some of the data of the first stream becomes invalidated over time and while a garbage collection service consolidates remaining valid data of the first stream together within the first segments, tracking the number of times the remaining valid data of the first stream is consolidated together within the first segments by the garbage collection service. The technique further involves comingling (i) remaining valid data of the first stream which has been consolidated together a predefined number of times within the first segments with (ii) the data of the other stream.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 14, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Nickolay Alexandrovich Dalmatov, Richard P. Ruef, Kurt W. Everson
  • Patent number: 10275313
    Abstract: A computing device of a dispersed storage network (DSN) includes a memory, interface and a processing module operable to identify an encoded data slice of the set of encoded data slices to produce an identified encoded data slice. The processing module generates a set of first write requests regarding the set of encoded data slices less the identified encoded data slice, and generates a set of second write requests regarding the identified encoded data slice. The set of second write requests include the identified encoded data slice and replications of the identified encoded data slice. The processing module sends the set of first write requests to storage units of the DSN, and sends the set of second write requests to a set of storage units of the DSN, where each storage unit of the set of storage units is sent a corresponding one of the set of second write requests.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Thomas Franklin Shirley, Jr., Gary W. Grube, Bart Cilfone, Ravi Khadiwala, Greg Dhuse, Thomas Darrel Cocagne, Michael Colin Storm, Yogesh Ramesh Vedpathak, Wesley Leggette, Jason K. Resch, Andrew Baptist, Ilya Volvovski
  • Patent number: 10275163
    Abstract: A host device coupled to a data storage device via a predetermined interface includes a processor and a signal processing device. The processor accesses data stored in the data storage device via the predetermined interface. The signal processing device performs signal processing on the data. The processor transmits a first power mode change request packet to the data storage device via the predetermined interface, to request to change a data transfer speed of the predetermined interface from a first speed to a second speed. The processor receives a first power mode change confirm packet via the predetermined interface from the data storage device, and in response to the first power mode change confirm packet, the processor determines to keep the data transfer speed at the first speed and does not change the data transfer speed to the second speed.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: April 30, 2019
    Assignee: SILICON MOTION, INC.
    Inventors: Fu-Jen Shih, Yen-Hung Chen
  • Patent number: 10255131
    Abstract: A storage device is provided. The storage device includes a nonvolatile memory device including memory blocks, and a controller configured to perform write, read and erase operations with respect to a selected memory block from among the memory blocks. If the number of error bits is greater than a critical value in a read operation with respect to the selected memory block, the controller is configured to perform a read reclaim of migrating valid data stored in the selected memory block to another memory block through at least two migration operations. In the read reclaim, the controller is configured to adjust an amount of data migrated in one migration operation.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: April 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: SeongCheol Hong, SongHo Yoon
  • Patent number: 10255182
    Abstract: A method of managing a cache includes storing first data of an upper level cache in a lower level cache, predicting a reuse distance level of second data having a same signature as the first data based on access information about the first data, and storing the second data in one of the lower level cache and a main memory based on the predicted reuse distance level of the second data.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: April 9, 2019
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Namhyung Kim, Junwhan Ahn, Kiyoung Choi, Woong Seo
  • Patent number: 10255199
    Abstract: Secure memory paging technologies are described. Embodiments of the disclosure may include checking attributes of secure page cache map to determine whether a target page to be evicted is clean and replay protected by a unified version-paging data structure and checking the unified version-paging data structure to determine whether contents of the unified version-paging data structure match the target page. When the target page to be evicted is clean and replay protected and the contents match, the target page can be removed without encrypting the contents of the target page.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Krystof C. Zmudzinski, Carlos V. Rozas