Abstract: A method, system and apparatus for protecting against out-of-bounds references, including storing an address of a buffer in a general register and storing bounds information (BI) for the buffer in a bounds information register, and when a content of the general register is used as an address in a load or store operation, using a content of the bounds information register to determine if the load or store is out of bounds.

Abstract: A memory system includes a memory device and a controller. The memory device includes plural storage regions including plural non-volatile memory cells. The plural storage regions have a different data input/output speed. The controller is coupled to the memory device via at least one data path. The controller performs a readahead operation in response to a read request input from an external device, determines a data attribute regarding readahead data, obtained by the readahead operation, based on a time difference between reception of the read request and completion of the readahead operation, and stores the readahead data in one of the plural storage regions based on the data attribute.

Abstract: A data operation method of a memory system is provided. The method includes, based on an obtained logical to physical mapping table, determining whether address values of a plurality of target physical addresses in the logical to physical mapping table corresponding to a plurality of target logical addresses are continuous; if so, selecting one of the plurality of target physical addresses as a base physical address, and setting a base physical address offset based on address values of remaining target physical addresses; and storing the base physical address and the base physical address offset into a cache of a memory controller, as a mapping relationship of the plurality of target logical addresses corresponding to the plurality of target physical addresses.

Abstract: A data storage method and apparatus includes receiving a data write request, where the data write request carries to-be-written data, and the to-be-written data includes at least one data block; calculating a fingerprint of each data block, where the fingerprint uniquely identifies the data block; determining whether the fingerprint of each data block exists in a fingerprint list, where the fingerprint list includes a fingerprint corresponding to a data block stored in a high-speed storage medium and a fingerprint corresponding to a data block stored in a low-speed storage medium; and performing a deduplication operation on the to-be-written data.

Abstract: A processor configured for real-time transaction processing is disclosed. A processor circuit includes configuration registers that designate a first range of physical memory addresses as reserved for real-time memory requests and a second, non-overlapping range of physical memory addresses that are shared between real-time and non-real-time memory requests. In response to determining that a memory request is associated with an address in the first range, the processor tags the request as a real-time request. The configuration registers may also store information designating portions of one or more cache memories and one or more buffers as being reserved for real-time memory requests. During arbitration, real-time memory requests are given priority over older, non-real-time memory requests.

Abstract: A host includes: an index tree storing an index including information for identifying a versioning key; and an index update buffer storing a write key included in data subject to a write request and the versioning key corresponding to the write key. When a preset update condition is satisfied, the host transfers the versioning key stored in the index update buffer to the index tree, and when the index update buffer requires recovery, the host designates a recovery section of memory of the storage device including data corresponding to the versioning key which has not been updated to the index tree, to be read by a plurality of threads, reads data included in the recovery section from the storage device through the plurality of threads, and inserts the read data into the index update buffer to recover the index update buffer.

Abstract: A processor includes a cache having two or more test regions and a larger non-test region. The processor further includes a cache controller that applies different cache replacement policies to the different test regions of the cache, and a performance monitor that measures performance metrics for the different test regions, such as a cache hit rate at each test region. Based on the performance metrics, the cache controller selects a cache replacement policy for the non-test region, such as selecting the replacement policy associated with the test region having the better performance metrics among the different test regions. The processor deskews the memory access measurements in response to a difference in the amount of accesses to the different test regions exceeding a threshold.

Abstract: A semiconductor memory and a method for density configuration of a bank of the semiconductor memory are provided. The method includes: determining a target bank to be configured of the semiconductor memory; determining a density configuration parameter of the target bank, the density configuration parameter being configured to represent a density to be configured for the target bank; determining a target code from a set of codes of the target bank based on the density configuration parameter of the target bank, the target code corresponding to a storage region to be trimmed in the target bank; generating, based on the target code, a region selection signal configured to select the storage region to be trimmed in the target bank; and trimming the storage region to be trimmed based on the region selection signal to configure the density of the target bank.

Abstract: According to certain embodiments, an electronic device comprises: a memory; and a processor operatively coupled to the memory, wherein the processor is configured to: identify a remaining capacity of the memory, and when the remaining capacity of the memory is less than a specified ratio of a total capacity of the memory, block compilation using a profile of an application, or delete an artifact created through compilation using the profile of the application.

Abstract: An electronic device includes a cache, a memory, and a controller. The controller stores an epoch counter value in metadata for a location in the memory when a cache block evicted from the cache is stored in the location. The controller also controls how the cache block is retained in the cache based at least in part on the epoch counter value when the cache block is subsequently retrieved from the location and stored in the cache.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.

Abstract: Disclosed are various embodiments for garbage collection for object-based storage systems. A first set of objects stored by an object storage service that have been accessed within a previously defined date range is identified. Then, a second set of objects stored by the object storage service is identified based at least in part on a relationship to one or more objects in the first set of objects. Next, a third set of objects stored by the object storage service that have been created prior to a predefined date is identified. Then, a subset of objects which are members of the third set of objects and not members of the first set of objects or the second set of objects is identified. Finally, a retention action is performed on individual members of the subset of objects based at least in part on a retention policy.

Abstract: Device, system, and method of determining memory requirements and tracking memory usage. A method includes: dynamically modifying, in an iterative process including two or more iterations, a maximum size of Random Access Memory (RAM) that a Memory Protection Unit (MPU) authorizes an executable program code to access. In each iteration, the method includes running that executable program code while the MPU enforces a different maximum size of RAM, and monitoring whether the executable program code attempted to access a RAM memory address that is beyond that maximum size of RAM in that iteration. Based on such iterations, the method determines a minimum size of RAM that is required for that executable program code to run without causing a memory access fault.

Abstract: A method of cache management, the method comprising: identifying, among a plurality of storage items, storage items having an access count above a first threshold to generate a set of storage items; identifying, among the set of storage items, storage items having an updated access count above a second threshold to generate a subset of storage items, wherein, for each storage item, the updated access count is dependent upon a number of accesses subsequent to generating the set of storage items; and adding the storage items of the subset of storage items to a cache.

Abstract: A first node receives a read request, determines a storage drive location where data corresponding to one or more logical addresses designated in the read request is stored, and requests transfer of the data at the one or more logical addresses, from the second node, when the storage drive location is the second node. The second node reads a data chunk containing the data designated by the one or more logical addresses, from one or more storage drives, determines whether to decompress the data chunk based on the size of the data chunk and the size of the one or more logical addresses, decompresses the data chunk based on the determination as to decompress the data chunk, extracts data at the one or more logical addresses, and transfers the extracted data to the first node.

Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink. The passive crosslink is a passive interposer die dedicated for inter-chiplet communications and partitions systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

Abstract: a method and an apparatus for managing a cache for storing content by determining popularity of the content based on content requests received during a current time slot for the content; transmitting information about the popularity of the content to a time-to-live (TTL) controller and receiving, from the TTL controller, TTL values for each popularity level determined by the TTL controller based on the information about the popularity; and managing the content based on the TTL values for each popularity level are provided.

Abstract: A memory control apparatus controls access to a DRAM having a plurality of banks. The apparatus comprises a first generating unit configured to generate an access command in accordance with an access request for the DRAM and store the access command in a buffer; a second generating unit configured to generate a bank-designated refresh request for the DRAM; and an issuing unit configured to issue a DRAM command to the DRAM based on an access command stored in the buffer and a refresh request generated by the second generating unit. The second generating unit determines a bank for which the refresh request is generated, based on an access time for each bank of the DRAM by not less than one access command stored in the buffer.

Abstract: A multi-port memory device in communication with a controller includes a memory array for storing data provided by the controller, a first port coupled to the controller via a first controller channel, a second port coupled to the controller via a second controller channel, a processor, and a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to: enable data transfer through the first port and/or the second port in response to a first control signal received from the first controller channel and/or a second control signal received from second controller channel, decode at least one of the received first and second control signals to identify a data operation to perform, the identified data operation including a read or write operation from or to the memory array, and execute the identified data operation.

Abstract: Embodiments of the present disclosure describe a memory reclaiming method and a terminal. As discussed with respect to the embodiments described herein, the method may include determining, by a terminal according to a preset rule, a target application program in application programs run on a background, where the target application program is an application program that needs to be cleaned. The method may also include freezing, by the terminal, the target application program, and reclaiming data generated during running of a process of the target application program in memory. The method may also include unfreezing, by the terminal when receiving an input triggering instruction for the target application program, the target application program, and running the target application program.