Abstract: Techniques are provided within a mapped RAID (Redundant Array of Independent Disks) system for assigning RAID extents to partnership groups and changing drive extent indications within RAID extents when splitting a group of storage drives into partnership groups. RAID extents are assigned to a RAID extent group corresponding to a newly created partnership group from a subset of RAID extents that contain RAID extents indicating higher total numbers of drive extents located in the physical data storage devices contained in the partnership group. When changing drive extent indications in RAID extents, new drive extents may be allocated to replace drive extents located outside of a partnership group such that a resulting variance in the values of a neighborhood matrix for the partnership group is minimized, to ensure that RAID extents are evenly distributed across the drives in the corresponding partnership group, to prevent drive rebuild performance from being compromised.

Abstract: Data storage is provided which includes a nonvolatile memory device including a plurality of memory blocks divided into a first region being an over provisioning region and a second region, and a storage controller allocating at least one memory block, corresponding to an unconcerned sector, from among memory blocks of the second region to the first region. It may be possible to adjust the number of reserved memory blocks in the over provisioning region.

Abstract: Provided is a method for mapping a logical address to a physical address, including: identifying whether a logical address is identical to a round value; mapping the logical address to a first physical address identical to an interval value when the logical address is identical to the round value; mapping the logical address to a second physical address corresponding to a value obtained by subtracting the round value from the logical address when the logical address is different from the round value; and adjusting a mapping value of the logical address to the second physical address to a value obtained by subtracting one from the second physical address when the second physical address is less than or equal to the interval value.

Abstract: Data synchronization between memories of a data processing system is achieved by transferring the data blocks from a first memory to a second memory, forming a hash list from addresses of data blocks that are written to the second memory or modified in the second memory. The hash list may be to identify a set of data blocks that are possibly written to or modified. Data blocks that are possibly modified may be written back from the second memory to the first memory in response to a synchronization event. The hash list may be updated by computing, in hardware or software, hash functions of an address of the transferred or modified data block to determine bit positions to be set. The hash list may be queried by computing hash functions of an address to determine bit positions, and checking bits in the hash list at those bit positions.

Abstract: Methods of mapping memory cells to applications, methods of accessing memory cells, systems, and memory controllers are described. In some embodiments, a memory system including multiple physical channels is mapped into regions, such that any region spans each physical channel of the memory system. Applications are allocated memory in the regions, and performance and power requirements of the applications are associated with the regions. Additional methods and systems are also described.

Abstract: The system includes host computers, file servers and a storage system having automated page-based management means. The storage system interface receives instructions to change the condition for decision for migration regarding particular parts or the whole volume. The host computer can control execution of the migration performed by the storage system by specifying areas or volumes with the condition via the interface. Highly optimized, appropriate data placement and data relocation in computer system can be achieved when the application, host computer or management computer can recognize or predict the usage of the data or files. The storage system having automated page-based management may include compression/decompression and a control method for the compression and decompression process.

Abstract: The described embodiments include a computer system having a multi-level memory hierarchy with two or more levels of memory, each level being one of two or more types of memory. The computer system handles storing objects in the multi-level memory hierarchy. During operation, a system runtime in the computer system identifies an object to be stored in the multi-level memory hierarchy. The system runtime then determines, based on one or more attributes of the object, that the object is to be pinned in a level of the multi-level memory hierarchy. The system runtime then pins the object in the level of the multi-level memory hierarchy. In the described embodiments, the pinning includes hard pinning and soft pinning, which are each associated with corresponding retention policies for pinned objects.

Abstract: In one example, a method includes generating an enhanced copy, which includes application data generated from using an application, the application, a configuration of the application and runtime settings to run the application. The method also includes restoring at least one of the application, the configuration of the application and the runtime settings using the enhanced copy.

Abstract: Low power DRAM (LPDRAM) memory devices for communication with a non-volatile memory coupled to the LPDRAM memory device, and systems containing such LPDRAM and non-volatile memory facilitate configuring the LPDRAM memory device using routines stored on the non-volatile memory.

Abstract: A method and information processing system with improved cache organization is provided. Each register capable of accessing memory has associated metadata, which contains the tag, way, and line for a corresponding cache entry, along with a valid bit, allowing a memory access which hits a location in the cache to go directly to the cache's data array, avoiding the need to look up the address in the cache's tag array. When a cache line is evicted, any metadata referring to the line is marked as invalid. By reducing the number of tag lookups performed to access data in a cache's data array, the power that would otherwise be consumed by performing tag lookups is saved, thereby reducing power consumption of the information processing system, and the cache area needed to implement a cache having a desired level of performance may be reduced.

Abstract: A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.

Abstract: Example devices are disclosed. For example, a device may include a processor, a plurality of translation lookaside buffers, a plurality of switches, and a memory management unit. Each of the translation lookaside buffers may be assigned to a different process of the processor, each of the plurality of switches may include a register for storing a different process identifier, and each of the plurality of switches may be associated with a different one of the translation lookaside buffer buffers. The memory management unit may be for receiving a virtual memory address and a process identifier from the processor and forwarding the process identifier to the plurality of switches. Each of the plurality of switches may be for connecting the memory management unit to a translation associated with the switch when there is a match between the process identifier and the different process identifier stored by the register of the switch.

Abstract: Example implementations may relate to a version controller allocating a copy page in persistent memory upon receiving, from an application executing on a processor, a copy command to version an image page for an atomic transaction. The version controller may receive application data addressed to a cache line of the image page, and may write the application data to a cache line of the copy page corresponding to the addressed cache line of the image page. If the version controller receives a replace-type transaction commit command, the version controller may generate a final page by either forward merging the image page into the copy page or backward merging the copy page into the image page, depending a merge direction policy.

Abstract: An operable mechanism implements a stub utility to facilitate the migration of stub files, where the stub utility is integrated with a data storage product and a data storage technique of an existing storage site containing the stub files. The stub utility identifies the stub files and uses virtualization to migrate the stub files to a new storage site without concomitantly recalling or accessing source files linked to the stub files.

Abstract: A method of processing transactions associated with a command in a storage system is provided. The method includes receiving, at a first authority of the storage system, a command relating to user data. The method includes sending a transaction of the command, from the first authority to a second authority of the storage system, wherein a token accompanies the transaction and writing data in accordance with the transaction as permitted by the token into a partition that is allocated to the second authority in a storage device of the storage system.

Abstract: A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

Abstract: A datum to be preloaded includes the acquisition of a, so-called “model”, statistical distribution of the deltas of a model access sequence, the construction of a, so-called “observed”, statistical distribution of the deltas of an observed access sequence, the identification in the observed statistical distribution, by comparing it with the model statistical distribution, of the most deficient class, that is to say of the class for which the difference NoDSM?NoDSO is maximal, where NoDSM and NoDSO are the numbers of occurrences of this class that are deduced, respectively, from the model statistical distribution and from the observed statistical distribution, the provision as prediction of the datum to be preloaded into the cache memory, of at least one predicted address where the datum to be preloaded is contained, this predicted address being constructed on the basis of the most deficient class identified.

Abstract: Systems and methods for list retrieval in a storage device are provided that significantly reduces the number of commands needed to retrieve data. A single command or request may be issued to receive data stored at a parent node, a child node, and/or a grandchild node. For example, a request may be issued that includes a node corresponding to a particular level, a depth level below that particular level to which to obtain data and/or filter criteria. With this information, the requested information may be obtained to the depth level while filtering out information not included in the request. When the request corresponds to a parent node and information about the children nodes is desired, for example, additional requests are not needed to obtain information from all of the parent node and the children nodes. Thus, the length of time needed to provide certain stored management information is reduced.

Abstract: Described are a system and technique for collecting stack trace information of devices and analyzing this information to provide metrics with respect to memory usage. The memory analysis includes attributing the memory usage to particular development components by traversing a stack trace. For example, the development components may correspond to a classification used for a particular development effort such as a group of classes, a sub-project, or a development team. As a result, the system may produce various metrics that produce memory usage information attributable to a more meaningful conceptual unit rather than, for example, function names. Accordingly, these attributions may be analyzed for forensic purposes to get a more meaningful picture of sources and causes of memory usage.

Abstract: An operable mechanism implements a stub utility to facilitate the migration of stub files, where the stub utility is integrated with a data storage product and a data storage technique of an existing storage site containing the stub files. The stub utility identifies the stub files and uses virtualization to migrate the stub files to a new storage site without concomitantly recalling or accessing source files linked to the stub files.