Abstract: An operable mechanism implements a stub utility to facilitate the migration of stub files, where the stub utility is integrated with a data storage product and a data storage technique of an existing storage site containing the stub files. The stub utility identifies the stub files and uses virtualization to migrate the stub files to a new storage site without concomitantly recalling or accessing source files linked to the stub files.

Abstract: A technique for data roll-back includes in response to a first external static memory device being coupled to a first chassis management module and the first chassis management module being coupled to a middle plane board, determining whether the first external static memory device operates normally. In response to the first external static memory device operating normally, a controller of the first chassis management module writes data in the first external static memory device into a non-volatile memory of the first chassis management module to perform data roll-back.

Abstract: A program controls coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. Optimized machine instructions are generated based on an intermediate representation of a program, wherein either two atomic tasks are merged into a single coalesced transaction or are executed as separate transactions.

Abstract: A method for deduplication rehydration is described. In one embodiment, a request to restore a backup image is received. The backup image is stored in a deduplication system. The backup image includes a plurality of data segments. The method includes determining locality information for at least one of the plurality of data segments. The locality information includes information regarding a location of the at least one data segment in relation to each other data segment of the plurality of data segments in the backup image. The method includes obtaining an identifier of each data container storing the plurality of data segments of the backup image, determining a degree to which the plurality of data segments of the backup image are processed by prefetching, and prefetching one or more of the plurality of target data segments from a data container based at least in part on a predetermined effectiveness threshold.

Abstract: Resources of an address space are managed in dynamically sized ranges, extents, sets, and/or blocks. The address space may be divided into regions, each corresponding to a different, respective allocation granularity. Allocating a block within a first region of the address space may comprise allocating a particular number of logical addresses (e.g., a particular range, set, and/or block of addresses), and allocating a block within a different region may comprise allocating a different number of logical addresses. The regions may be configured to reduce the metadata overhead needed to identify free address blocks (and/or maintain address block allocations), while facilitating efficient use of the address space for differently sized data structures.

Abstract: Techniques described herein generally include methods and systems related to designing and operating a DRAM device that has significantly reduced refresh energy use. A method for designing a DRAM optimizes or otherwise improves the DRAM for energy efficiency based on a measured or predicted failure probability of memory cells in the DRAM. The DRAM may be configured to operate at an increased refresh interval, thereby reducing DRAM refresh energy but causing a predictable portion of the memory cells in the DRAM to leak electrical energy too quickly to retain data. The DRAM is further configured with a selected number of spare memory cells for replacing the “leaky” memory cells, so that operation of the DRAM at the increased refresh interval may result in little or no reduction in capacity of the DRAM.

Abstract: In one embodiment, the method includes receiving a read request for reading data from a memory area of the memory, and determining whether an identifier of the memory area is stored in one of the plurality of entries of a characteristic table. Each of the plurality of entries is associated with a different range of at least one memory area characteristic and each of the plurality of entries is associated with different read condition information. The method further includes obtaining the read condition information associated with the entry storing the identifier of the memory area if the determining determines the identifier is stored in one of the plurality of entries of the characteristic table, and controlling the memory to read data from the memory area using the obtained read condition information.

Abstract: A system for data processing with management of a cache consistency in a network of processors including cache memories, the network including plural nodes for access to a main memory interconnected with one another, a set of directories being distributed between nodes of the network, each directory including a table of correspondence between cache lines and information fields on the cache lines. The system includes a first sub-network for interconnection of the nodes with one another, implementing a first message transmission protocol providing read/write access to the directories during any passage in the corresponding nodes of a message passing through the first sub-network, and a second sub-network for interconnection of the nodes with one another, implementing a second message transmission protocol, the second protocol excluding any read/write access to the directories during any passage in the corresponding nodes of a message passing through the second sub-network.

Abstract: Methods and systems for managing resources in a storage system are provided. The methods include tracking performance of a plurality of resources used for reading and writing information at storage devices in a networked storage system, each resource represented by a logical object in a hierarchical structure and performance data associated with each logical object is maintained by a processor executing a management application out of a memory device; identifying a root object associated with a resource having a performance issue as indicated by a threshold violation for the resource; selecting a related object associated with a resource similar to the resource of the root object by the management application for comparing performance data of the root object with the related object; and using the comparison to verify that the root object is a root cause of the performance issue.

Abstract: Methods and apparatus for termination of signal lines coupled to a number of memory devices are disclosed. One such method includes adjusting an input impedance of one or more terminals of an interface of a memory device in response to the memory device receiving a particular address. One such apparatus includes memory devices configured to selectively adjust an input impedance seen by one or more of the signal lines in response to receiving a particular address.

Abstract: A chip multiprocessor includes a plurality of cores each having a translation lookaside buffer (TLB) and a prefetch buffer (PB). Each core is configured to determine a TLB miss on the core's TLB for a virtual page address and determine whether or not there is a PB hit on a PB entry in the PB for the virtual page address. If it is determined that there is a PB hit, the PB entry is added to the TLB. If it is determined that there is not a PB hit, the virtual page address is used to perform a page walk to determine a translation entry, the translation entry is added to the TLB and the translation entry is prefetched to each other one of the plurality of cores.

Abstract: Systems and methods to safely and efficiently handle dirty data flush are disclosed. More specifically, when a cache controller determines that one (or more) storage device of a cache device is running out of space, that storage device is given priority to be flushed prior to the other storage devices that are not in such a critical condition. In addition, a cache bypass process can be conditionally enabled to save free physical spaces already running low on such critical cache storage devices.

Abstract: Efficient techniques are described for reducing cache pollution by use of a prefetch logic that recognizes exits from software loops or function returns to cancel any pending prefetch request operations. The prefetch logic includes a loop data address monitor to determine a data access stride based on repeated execution of a memory access instruction in a program loop. Data prefetch logic then speculatively issues prefetch requests according to the data access stride. A stop prefetch circuit is used to cancel pending prefetch requests in response to an identified loop exit. The prefetch logic may also recognize a return from a called function and cancel any pending prefetch request operations associated with the called function. When prefetch requests are canceled, demand requests, such as based on load instructions, are not canceled. This approach to reduce cache pollution uses program flow information to throttle data cache prefetching.

Abstract: A method for making memory more reliable involves accessing data stored in a removable storage device by translating a logical memory address provided by a host digital device to a physical memory address in the device. A logical memory address is received from the host digital device. The logical memory address corresponds to a location of data stored on the removable storage device. A physical memory address corresponding to the local address is determined by accessing a lookup table corresponding to the logical zone.

Abstract: A non-transitory computer-readable recording medium has stored therein a program that causes a computer to execute a control process. The control process includes: receiving an access request for a recording device that stores data; determining whether or not index information corresponding to the access request, which is received at the receiving, is stored in a memory that stores index information that is obtained by shortening identification information identifying data from the recording device cached in a non-volatile memory; and accessing the non-volatile memory when it is determined that the index information is stored in the memory and accessing the recording device when it is determined that the index information is not in the memory.

Abstract: According to an embodiment, when data read from a first storage unit which is a backup source is not identical with data indicated by a first function, the read data is written to a second storage unit which is a backup destination. When the data read from the first storage unit is identical with the data indicated by the first function, the read data is not written to the second storage unit and a deletion notification is sent to the second storage unit.

Abstract: A memory controller for heterogeneous computer processors dynamically adjusts access priorities by the different processors to maximize performance in the execution of a single parallel application program on both processor architectures. In one embodiment, the memory controller predicts sequential memory accesses by the processor having higher memory latency or fewer access requests to lockout the other processor during those sequences for improved implementation of the intended prioritization.

Abstract: The disclosure presents examples of a RAID storage system, method and computer program product where a stripe is logically partitioned into two or more sub-stripes and at least one RAID erasure code is applied to each sub-stripe independently of any other of the sub-stripe(s). Consequently, in some of these examples, a larger packet size may be used than if the stripe had not been partitioned. A larger packet size may in some cases allow for accelerated encoding and/or decoding.

Abstract: A system and method is described for operating a computer memory system having a plurality of controllers capable of accessing a common set of memory modules. Access to the physical storage of the memory modules may be managed by configuration logical units (LUNs) addressable by the users. The amount of memory associated with each LUN may be managed in units of memory (LMA) from a same free LMA table maintained in each controller of the plurality of controllers. A request for maintenance of a LUN may be received from any user through any controller and results in the association of a free memory area with the LUN, and the remaining controllers perform the same operation. A test for misallocation of a free memory area is performed and when such misallocation occurs, the situation is corrected in accordance with a policy.

Abstract: Techniques are disclosed relating to arranging data on storage media. In one embodiment, a computer system is configured to access a storage array that includes a plurality of storage blocks. The computer system executes a first set of processes and a second set of processes, where the first set of processes operates on selected ones of the plurality of storage blocks to increase a likelihood that the selected storage blocks are operated on by the second set of processes. In some embodiments, the second set of processes determines whether to operate on a storage block based on an amount of invalid data within the storage block. In such an embodiment, the first set of processes increases a likelihood that the storage block is operated on by increasing the amount of invalid data within the storage block.