Abstract: A semiconductor device including a plurality of wirings and an insulating space is described. The insulating space is disposed between adjacent wirings of the plurality of wirings. An insulating material surrounds the insulating space. The insulating space is filled with air at a pressure no more than an atmospheric pressure.

Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first liner. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through-via, and forming conductive features on opposing sides of the semiconductor substrate. The conductive features are electrically interconnected through the through-via.

Abstract: According to various examples, a semiconductor package is described including a substrate raiser with interconnect vias that may be positioned on the bottom side of a substrate and mini solder balls positioned on the interconnect vias and a plurality of large solder balls positioned on the bottom side of the substrate adjacent to the substrate raiser, wherein the mini solder balls and the large solder balls extend approximately a same height from the substrate for mounting on a printed circuit board.

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Abstract: Provided is a coloring pattern structure. The coloring pattern structure includes: a substrate; a light-transmitting dielectric layer formed on at least one surface of the substrate; and a composite material layer disposed on an upper surface of the light-transmitting dielectric layer and formed of a metal and a first material not having a thermodynamic solid solubility in the metal, wherein the metal included in the composite material layer has a pattern coated only on portions of the upper surface of the light-transmitting dielectric layer, and the first material is coated on the remaining area where the metal is not coated.

Abstract: A semiconductor chip may include: a body portion including a front surface and a back surface; penetrating electrodes penetrating the body portion; and back connection electrodes disposed over the back surface of the body portion and connected to the penetrating electrodes, wherein the penetrating electrodes include a power penetrating electrode for transmitting a power voltage and a ground penetrating electrode for transmitting a ground voltage, the back connection electrodes include a power back connection electrode connected to the power penetrating electrode and a ground back connection electrode connected to the ground penetrating electrode, and one power back connection electrode is connected with two or more power penetrating electrodes, and one ground back connection electrode is connected with two or more ground penetrating electrodes.

Abstract: The present invention provides a mask, a display panel, a method for manufacturing a display panel, and a display device. The display panel has a hollow region and a display region surrounding the hollow region. The display panel includes a plurality of organic light-emitting devices arranged only in the display region. Each of the plurality of organic light-emitting devices includes an anode layer, a cathode layer, a light-emitting layer and a functional layer. The functional layer includes a plurality of uneven portions.

Abstract: Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.

Abstract: A vapor deposition mask includes a mask main body and a support joined to the mask main body. The mask main body has a first alignment mark whereas the support has a second alignment mark. The first alignment mark and the second alignment are provided at such positions as to overlap with each other in plan view, and either one of the alignment marks is larger than the other of the alignment marks.

Abstract: An electric field drives nanocrystals dispersed in solvents to assemble into ordered three-dimensional superlattices. A first electrode and a second electrode 214 are in the vessel. The electrodes face each other. A fluid containing charged nanocrystals fills the vessel between the electrodes. The electrodes are connected to a voltage supply which produces an electrical field between the electrodes. The nanocrystals will migrate toward one of the electrodes and accumulate on the electrode producing ordered nanocrystal accumulation that will provide a superlattice thin film, isolated superlattice islands, or coalesced superlattice islands.

Abstract: An apparatus and method of processing a workpiece is disclosed, where a sacrificial capping layer is created on a top surface of a workpiece. That workpiece is then exposed to an ion implantation process, where select species are used to passivate the workpiece. While the implant process is ongoing, radicals and excited species etch the sacrificial capping layer. This reduces the amount of etching that the workpiece experiences. In certain embodiments, the thickness of the sacrificial capping layer is selected based on the total time used for the implant process and the etch rate. The total time used for the implant process may be a function of desired dose, bias voltage, plasma power and other parameters. In some embodiments, the sacrificial capping layer is applied prior to the implant process. In other embodiments, material is added to the sacrificial capping layer during the implant process.

Abstract: A display substrate includes a supporting material layer having at least one flexible material sub-layer and at least one blocking sub-layer, which can be alternately and successively arranged in layers. One blocking sub-layer is at a topmost sub-layer of the supporting material layer, and is provided with a well, located in a display area and configured for accommodating a display component therewithin. One or more of the at least one flexible material sub-layer or the at least one blocking sub-layer is configured as a target material layer. The target material layer includes a planar portion and a protruding portion over the planar portion. An orthographic projection of the protruding portion on a bottom surface of the supporting material layer forms a ring-like structure having an opening that covers an orthographic projection of a bottom surface of the well on the bottom surface of the supporting material layer.

Abstract: The present invention relates to the field of display technology, and discloses a method for preparing an array substrate, a display panel and an evaporation apparatus. A method for preparing an array substrate comprises: fixing a base substrate to an evaporation stage; attaching a shielding sheet to the base substrate to cover at least a preset area of the base substrate; arranging and aligning an open mask in association with the base substrate; and evaporating to form a evaporation material layer on the base substrate, to which the shielding sheet is attached, with the open mask.

Abstract: A nitride semiconductor device is disclosed. The semiconductor device is formed by a process that first deposits a silicon nitride (SiN) film on a semiconductor layer by the lower pressure chemical vapor deposition (LPCVD) technique at a temperature, then, forming an opening in the SiN film for an ohmic electrode. Preparing a photoresist on the SiN film, where the photoresist provides an opening that fully covers the opening in the SiN film, the process exposes a peripheral area around the opening of the SiN film to chlorine (Cl) plasma that may etch the semiconductor layer to form a recess therein. Metals for the ohmic electrode are filled within the recess in the semiconductor layer and the peripheral area of the SiN film. Finally, the metals are alloyed at a temperature lower than the deposition temperature of the SiN film.

Abstract: A method of manufacturing a semiconductor device includes forming a base layer on a substrate. A structure layer is Conned on the base layer. The structure layer includes at least one material layer. A structure pattern is formed on the base layer. The structure pattern includes a first trench extending in a first direction and a second trench having a cross portion extending in a second direction that is perpendicular to the first direction. The second trench is connected to the first trench. The structure pattern further includes a base pattern having a recess portion recessed downward from a surface of the base layer at the cross portion of the second trench.

Abstract: A display device includes a bending area at which the display device is bendable; an organic light emitting element disposed on the substrate; an encapsulation layer covering an upper surface and a side surface of the organic light emitting element; and a bending area protection layer covering the bending area of the substrate. The upper surface of the encapsulation layer includes a nano structure defined by nano sized protrusions and depressions of the upper surface, and along the substrate, and the bending area is disposed separated from the encapsulation layer.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first conductive layer positioned above the substrate, a bottom conductive layer positioned above the first conductive layer and electrically coupled to the first conductive layer, a programmable insulating layer positioned on the bottom conductive layer, a top conductive layer positioned on the programmable insulating layer, and a redistribution structure positioned above the first conductive layer and electrically coupled to the first conductive layer. The bottom conductive layer, the programmable insulating layer, and the top conductive layer together configure a programmable unit.

Abstract: The disclosure provides a film forming method that enables to obtain an epitaxial film with reduced defects such as dislocations due to a reduced facet growth industrially advantageously, even if the epitaxial film has a corundum structure. When forming an epitaxial film on a crystal-growth surface of a corundum-structured crystal substrate directly or via another layer, using the crystal substrate having an uneven portion on the crystal-growth surface of the crystal substrate, generating and floating atomized droplets by atomizing a raw material solution including a metal; carrying the floated atomized droplets onto a surface of the crystal substrate by using a carrier gas; and causing a thermal reaction of the atomized droplets in a condition of a supply rate limiting state.

Abstract: A method for commissioning a drilling rig. The method includes detecting a first plurality of components of a drilling rig control system to control a drilling operation, obtaining a knowledge graph comprising a plurality of nodes corresponding to the first plurality of components, and a plurality of links connecting the plurality of nodes, wherein each of the plurality of links represents at least a target measure of data communication and resource utilization of each pair of components of the first plurality of components, and performing, by a drilling rig commissioning system and based on the knowledge graph, a management task of the drilling rig control system.

Abstract: A method for preparing a SiC ingot includes: disposing a raw material and a SiC seed crystal facing each other in a reactor having an internal space; subliming the raw material by controlling a temperature, a pressure, and an atmosphere of the internal space; growing the SiC ingot on the seed crystal; and collecting the SiC ingot after cooling the reactor. The wafer prepared from the ingot, which is prepared from the method, generates cracks when an impact is applied to a surface of the wafer, the impact is applied by an external impact source having mechanical energy, and a minimum value of the mechanical energy is 0.194 J to 0.475 J per unit area (cm2).