Abstract: A substrate film forming machine table and a usage method. The substrate film forming machine table comprises: a first substrate bearing inlet and outlet chamber; a second substrate bearing inlet and outlet chamber; a film forming chamber; an intermediate chamber; a pump set connected to the first substrate bearing inlet and outlet chamber; a second pump connected to the intermediate chamber; a third pump connected to the film forming chamber and the second substrate bearing inlet and outlet chamber; at least one backup pump, which is provided to connect to the film forming chamber and the second substrate bearing inlet and outlet chamber so as to extract air from the film forming chamber and the second substrate bearing inlet and outlet chamber when the third pump is damaged; or, connecting to the intermediate chamber so as to extract air from the intermediate chamber when the second pump is damaged.

Abstract: The present disclosure provides a display substrate, a method for preparing the same, and a display device including the display substrate. The method includes: forming a conductive layer; forming a first photoresist pattern and a second photoresist pattern on the conductive layer, in which the adhesion between the first photoresist pattern and the conductive layer is less than the adhesion between the second photoresist pattern and the conductive layer; and etching the conductive layer by using the first photoresist pattern and the second photoresist pattern as masks to form a first conductive pattern and a second conductive pattern, respectively, in which a line width difference between the first conductive pattern and the first photoresist pattern is greater than a line width difference between the second conductive pattern and the second photoresist pattern.

Abstract: Molecular-beam epitaxy (MBE) and more particularly suboxide MBE (S-MBE) and related structures are disclosed. S-MBE is disclosed that includes the use of a molecular beam of a suboxide that may be subsequently oxidized in a single step reaction to form an oxide film. By way of example, for a gallium oxide (Ga2O3) film, a molecular beam including a suboxide of gallium (Ga2O) may be provided. S-MBE may be performed in adsorption-controlled regimes where there is an excess of source material containing species in order to promote high growth rates for oxide films with improved crystallinity. Source mixtures for providing molecular beams of suboxides are disclosed that include mixtures of a particular element and an oxide of the element in ratios that promote such adsorption-controlled growth regimes. Related structures include oxide films having increased thickness with reduced crystal defects, including single polymorph films of gallium oxide.

Abstract: An interconnect structure and an electronic apparatus including the interconnect structure are provided. The interconnect structure includes a conductive layer; a dielectric layer configured to surround at least a part of the conductive layer; and a diffusion barrier layer disposed between the conductive layer and the dielectric layer and configured to limit and/or prevent a conductive material of the conductive layer from diffusing into the dielectric layer, and at least one of the dielectric layer and the diffusion barrier layer includes a boron nitride layer of a low dielectric constant.

Abstract: A substrate includes a first base, a pixel defining layer and spacers. The pixel defining layer disposes above the first base and has a plurality of openings. The pixel defining layer includes a first pixel defining sub-layer and a second pixel defining sub-layer stacked in a direction away from the first base. The spacers dispose on a surface of the pixel defining layer facing away from the first base. The second pixel defining sub-layer includes a first conductive material doped at least in a surface of the second pixel defining sub-layer facing away from the first base, the spacers include a second conductive material doped at least in surfaces of the spacers facing away from the first base.

Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes a substrate having an electronic component. A substrate-based coil is on the substrate and the substrate-based coil is electrically coupled to the electronic component. A magnetic mold compound encapsulates the substrate-based coil and the electronic component.

Abstract: A top emission organic EL device includes an anode, hole transporting zone, emitting layer, electron transporting zone, and cathode in this order. The hole transporting zone includes: a first layer interposed between the anode and the emitting layer; and a second layer interposed between the first layer and the emitting layer. The first layer contains a first compound and the second layer contains a second compound. A film thickness of the first layer and the second layer satisfies a formula (1) and (2), respectively. A hole mobility ?H1 of the first compound satisfies a formula (3) and a hole mobility ?H2 of the second compound satisfies a formula (4), 100 nm?d1?300 nm??(1) 1 nm?d2?20 nm??(2) 1.0×10?4 [cm2/Vs]??H1?1.0×10?1 [cm2/Vs]??(3) 1.0×10?10 [cm2/Vs]??H2?1.0×10?6 [cm2/Vs]??(4).

Abstract: The present disclosure provides a method for forming semiconductor structures. The method includes providing a device having a substrate, a first dielectric layer over the substrate, and a first conductive feature over the first dielectric layer, the first conductive feature comprising a first metal, the first metal being a noble metal. The method also includes depositing a second dielectric layer over the first dielectric layer and covering at least sidewalls of the first conductive feature; etching the second dielectric layer to form a trench; and forming a second conductive feature in the trench. The second conductive feature comprises a second metal different from the first metal.

Abstract: A leadframe includes a die pad and a set of electrically conductive leads. A semiconductor die, having a front surface and a back surface opposed to the front surface, is arranged on the die pad with the front surface facing away from the die pad. The semiconductor die is electrically coupled to the electrically conductive leads. A package molding material is molded over the semiconductor die arranged on the die pad. A stress absorbing material contained within a cavity delimited by a peripheral wall on the front surface of the semiconductor die is positioned intermediate at least one selected portion of the front surface of the semiconductor die and the package molding material.

Abstract: A structure is provided and includes (i) a substrate having a surface, the surface comprising a ternary or quaternary oxide having a first lattice parameter, the first lattice parameter being a lattice parameter of the ternary or quaternary oxide as it is present at the surface; and (ii) a layer of a perovskite oxide on the ternary or quaternary oxide, the perovskite oxide having a second lattice parameter, the second lattice parameter being a native lattice parameter of the perovskite oxide, wherein the first lattice parameter is larger than the second lattice parameter. A method for forming a perovskite oxide with an a-axis orientation is also provided.

Abstract: A method of forming a semiconductor device includes forming a conductive feature and a first punch stop layer, where the conductive feature has a first top surface, and where the first punch stop layer has a second top surface that is substantially level with the first top surface. The method further includes forming a resistive element over the first punch stop layer. The method further includes etching through a first portion of the resistive element to form a first trench that exposes both the second top surface of the first punch stop layer and a first sidewall surface of the resistive element. The method further includes forming a first conductive via within the first trench, where the first conductive via contacts the first sidewall surface of the resistive element.

Abstract: Semiconductor devices with on-pitch vias, and associated systems and methods, are disclosed herein. In one embodiment, the semiconductor device may include a 3-dimensional (3D) cross-point memory array. The semiconductor device also includes access lines for the memory array, which couple with on-pitch vias connected to CMOS circuitry disposed underneath the memory array. In some embodiments, a first access line may be coupled with a first via outside a boundary of the memory array, where the first via is separated from the boundary by a first distance and has a first length longitudinal to the first access line. Further, a second access line may be coupled with a second via outside the boundary, where the second via is separated from the boundary by a second distance greater than the first distance and has a second length longitudinal to the second access line, the second length different from the first length.

Abstract: A package structure and a circuit layer structure are provided in the present disclosure. The package structure includes a wiring structure, a first electronic device, a second electronic device and at least one dummy trace. The wiring structure includes a plurality of interconnection traces. The first electronic device and the second electronic device are disposed on the wiring structure, and electrically connected to each other through the interconnection traces. The dummy trace is adjacent to the interconnection traces. A mechanical strength of the at least one dummy trace is less than a mechanical strength of one of the interconnection traces.

Abstract: A multi-layer device comprising a barrier or adhesion layer located on a portion of a first top surface of a first layer, a conductive metal layer located on barrier or adhesion layer; and a dielectric layer located on top of the first layer, wherein the dielectric layer is in direct contact with the sidewall of the conductive metal layer.

Abstract: An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.

Abstract: A semiconductor device includes a substrate, an isolation feature, a floating gate, and a control gate. The substrate has a protruding portion. The isolation feature surrounds the protruding portion of the substrate. The floating gate is over the protruding portion of the substrate, in which a sidewall of the floating gate is aligned with a sidewall of the protruding portion of the substrate. The control gate is over the floating gate.

Abstract: A semiconductor memory device and a device including the same are provided. The semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate; bit line structures extending across the word lines in a second direction crossing the first direction; contact pad structures between the word lines and between the bit line structures; and spacers between the bit line structures and the contact pad structures. The spacers include a boron nitride layer.

Abstract: Provided is a semiconductor package including a redistribution substrate, a connection substrate on the redistribution substrate, the connection substrate having an opening that penetrates the connection substrate, a semiconductor chip in the opening of the connection substrate, and a molding layer that covers the semiconductor chip and the connection substrate, and fills a space between the semiconductor chip and the connection substrate, the connection substrate includes a base layer, a plurality of vias that vertically penetrate the base layer, a plurality of first patterns on a top surface of the base layer and connected to the plurality of vias, and a plurality of second patterns on a bottom surface of the base layer and connected to the plurality of vias, an extension of the molding layer extends into a plurality of holes that are spaced apart from the plurality of vias and are formed to vertically penetrate the base layer.

Abstract: An electronic device is provided. The electronic device includes a substrate and an electronic unit disposed on the substrate. The electronic unit includes a light-emitting diode, a conductive structure, a first driving circuit, and a second driving circuit. The conductive structure is disposed between the light-emitting diode and the substrate. The first driving circuit includes a first output wire. The second driving circuit includes a second output wire. The first driving circuit is electrically connected to the light-emitting diode by the conductive structure. The second driving circuit is electrically insulated from the light-emitting diode. In addition, the conductive structure at least partially overlaps the first output wire and the second output wire in a normal direction of the substrate.

Abstract: Embodiments of the present disclosure generally relate to a processing system for forming one or more layers of a photodiode. In one embodiment, the processing system includes a transfer chamber, a plurality of processing chambers, and a controller configured to cause a process to be performed in the processing system. The process includes performing a pre-clean process on a substrate, aligning and placing a first mask on the substrate, depositing a first layer on the substrate, and depositing a second layer on the substrate. The processing system can form layers of a photodiode in a low defect, cost effective, and high utilization manner.