Patents Examined by James H. Cho
  • Patent number: 10327311
    Abstract: Enhancements to ornamental or holiday lighting are disclosed including remote control ornamental illumination with color pallet control whereby a user can vary the color/intensity/appearance of an individual bulb or entire light string by selecting the electronic address of the bulb and selecting its attribute. Further disclosures include: motion responsive lights which respond to sensed movement, gesture controlled lights, adjustable white color/white led sets, connectable multi-function lights, controller to sequence lights to music or other input source, rotating projection led light/tree top/table top unit, and remote controlled sequencing icicle lights and ornament lighting system.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: June 18, 2019
    Assignee: Seasonal Specialties, LLC
    Inventors: Steven J. Altamura, Christine Werner, Derek Dean Anderson, Matthew Guse, Carmen Miller
  • Patent number: 10327298
    Abstract: An LED luminaire comprises a power switching driver, LED array(s) powered by the power switching driver, and a detection and control circuit. The detection and control circuit comprises a voltage sensing circuit, a current sensing circuit, a voltage regulator circuit, an optocoupler circuit, and a pair of low-voltage input ports receiving an external voltage. The detection and control circuit is configured to extract an electrical signal from an output voltage, an output current driving the LED array(s), and the external voltage and to couple an optical feedback signal to the power switching driver. The external voltage comprises a voltage sent from a motion sensor, an adapted control voltage from a daylight sensor, or both to control the power switching driver to offset lighting amount of the LED luminaire to reduce energy consumption in response to changing daylight availability when a motion is detected.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: June 18, 2019
    Assignee: ALEDDRA INC.
    Inventor: Chungho Hsia
  • Patent number: 10320388
    Abstract: A method for decoding a plurality of input signals in a plurality of dynamic decode circuits, each dynamic decode circuit sharing a conditioned node and comprising a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate.
    Type: Grant
    Filed: July 8, 2018
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul Alan Bunce, Yuen Hung Chan, John D Davis, Antonio Raffaele Pelella
  • Patent number: 10320390
    Abstract: A reconfigurable field programmable gate array (FPGA) includes: a first logic block having a first lookup table; and a second logic block having a second lookup table, wherein the first logic block is coupled to the second logic block, in which the first logic block is configured to pass, upon a clock cycle of the FPGA, data about a lookup table configuration stored in the first lookup table to the second logic block.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 11, 2019
    Inventor: Jonathan Ross
  • Patent number: 10317286
    Abstract: A luminaire comprises at least one light emitting diode (LED) as a light source. Such LED has a limited light emitting angle for emitted light radiation. An infrared sensor is assigned to the light source for determining the temperature of same.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: June 11, 2019
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventor: Toni Ott
  • Patent number: 10314123
    Abstract: An LED luminaire comprises a power switching driver, an electric current controller, LED array(s) powered by the electric current controller, and a detection and control circuit. The detection and control circuit comprises comparator(s), a voltage regulator circuit, and a pair of low-voltage input/output ports receiving an external voltage. The detection and control circuit is configured to extract a controllable feedback signal voltage from an output voltage coupled from the power switching driver, an output current driving the LED array(s), and the external voltage and to couple to the electric current controller to change the output current driving the LED array(s). The external voltage comprises a voltage sent from a wireless luminaire controller, which comprises a wireless module and a meter and control unit. The wireless luminaire controller is configured to receive commands from the wireless module, to control the LED luminaire, and to measure in response to the commands.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: June 4, 2019
    Assignee: ALEDDRA INC.
    Inventor: Chungho Hsia
  • Patent number: 10312888
    Abstract: Various embodiments of a robust double node upset tolerant latch in which all internal and external nodes are capable of recovering the previous value after a single event upset are disclosed.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: June 4, 2019
    Assignee: Board of Trustees of Southern Illinois University on Behalf of Southern Illinois University Carbondale
    Inventors: Adam Watkins, Spyros Tragoudas
  • Patent number: 10314130
    Abstract: System and method for providing at least an output current to one or more light emitting diodes. The system includes a control component configured to receive at least a demagnetization signal, a sensed signal and a reference signal and to generate a control signal based on at least information associated with the demagnetization signal, the sensed signal and the reference signal, and a logic and driving component configured to receive at least the control signal and output a drive signal to a switch based on at least information associated with the control signal. The switch is connected to a first diode terminal of a diode and a first inductor terminal of an inductor. The diode further includes a second diode terminal, and the inductor further includes a second inductor terminal.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: June 4, 2019
    Assignee: On-Bright Electronics (Shanghai) Co., Ltd.
    Inventors: Lieyi Fang, Jun Zhou
  • Patent number: 10312916
    Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises precharge circuits that consist of two serially connected transistors, that utilize an evaluate clock and a delayed evaluate clock, that delay the start of a precharge phase for a predetermined period after the end of an evaluation phase.
    Type: Grant
    Filed: July 8, 2018
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul Alan Bunce, Yuen Hung Chan, John D Davis, Antonio Raffaele Pelella
  • Patent number: 10312915
    Abstract: A method for a dynamic decode circuit to decode a plurality of input signals, the dynamic decode circuit comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive.
    Type: Grant
    Filed: July 8, 2018
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Paul Alan Bunce, Yuen Hung Chan, John D Davis, Antonio Raffaele Pelella
  • Patent number: 10305485
    Abstract: An object of the present invention is to provide a method for effectively performing characterization for circuit verification by static timing analysis, of a programmable logic integrated circuit including a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, wherein: the programmable logic integrated circuit is divided into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch; the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell; and circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 28, 2019
    Assignee: NEC CORPORATION
    Inventors: Ayuka Tada, Noboru Sakimura, Makoto Miyamura, Yukihide Tsuji, Ryusuke Nebashi, Xu Bai, Toshitsugu Sakamoto
  • Patent number: 10291414
    Abstract: An approach is provided in which an information handling system performs multiple tests on a memory device using different supply voltage levels. The information handling system identifies a set of memory cells in the memory that produce a same result during each of the memory tests at the different supply voltage levels, and generates a unique identifier based on the set of memory cells. In turn, the information handling system uses the unique identifier in one or more processes executed by the information handling system.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10284204
    Abstract: There are provided a logic unit circuit and a pixel driving circuit, which relate to a display technical field and are used to solve the problem that technical difficulties are increased due to mixed use of different types of transistors in the logic unit circuit. The logic unit circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor of a same type. The logic unit circuit is used to realize logic gate operation.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: May 7, 2019
    Assignees: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Xuehuan Feng, Bo Mao
  • Patent number: 10277228
    Abstract: A chip configured with pin-strapping includes a configuration pin coupled to a resistor, the resistor coupled a configuration circuit configured to provide a threshold voltage at a sense time interval. A configuration vector may be determined by driving the configuration pin with high impedance, and sampling the configuration pin at sense time intervals such that the configuration vector corresponds to the time interval at which a threshold voltage is reached.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: April 30, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventor: Bruce Douglas Buch
  • Patent number: 10270441
    Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: April 23, 2019
    Assignee: Rambus Inc.
    Inventors: Huy M. Nguyen, Vijay Gadde, Benedict Lau
  • Patent number: 10271391
    Abstract: A driver for generating an output voltage to power an LED having a minimum operating voltage VLED min, comprising: (a) a first voltage converting stage comprising an input terminal and an output terminal; (b) a charge storage device electrically connected to the output terminal and having a charge output voltage VC; (c) at least one second voltage converting stage having an input electrically connected to the charge storage device, the second voltage converting stage being configured to increase said VC to at least VLED min; and (d) at least one mode controller to switch between at least a first mode and a second mode, in the first mode, the first voltage converting stage charges the charge storage device to power the LED without substantial contribution from the second voltage converting stage, and, in the second mode, the second voltage converting stage power to the LED.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: April 23, 2019
    Assignee: SORAA, INC.
    Inventor: Laszlo Takacs
  • Patent number: 10262732
    Abstract: This disclosure introduces a programmable array logic (PAL) circuit and a method which are capable of preventing a read disturbance effect on memory cells of the PAL circuit. The PAL circuit comprises a memory array coupled to a plurality of input lines and a plurality of source lines, a plurality of input transition detection (ITD) circuits, a pulse generator and a plurality of sense amplifiers. The plurality of ITD circuits detect a transition in level of the plurality of input signals in the input lines. The pulse generator generates an enable signal according to the transition in level of the input signals. The sense amplifiers are enabled to sense the voltage levels of the source lines when the transition in levels of the input signals is detected, and the sense amplifiers are disabled when no transition in levels of the input signals is detected.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: April 16, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Seow Fong Lim, Chi-Shun Lin, Douk-Hyoun Ryu, Ngatik Cheung
  • Patent number: 10263619
    Abstract: An isolation cell clamps a signal passing from a first, powered-down power domain to a second, power-on power domain. To reduce leakage current, some of the circuits and devices are connected to a voltage supply of the first or “from” power domain, while other circuits and devices are connected to a voltage supply of the second or “to” power domain.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: April 16, 2019
    Assignee: NXP USA, INC.
    Inventors: Peidong Wang, Miaolin Tan, Zhe Ge
  • Patent number: 10256386
    Abstract: A light emitting device includes a substrate, a plurality of first wiring members, a plurality of second wiring members and a plurality of light emitting elements. The first wiring members extend in a first direction. The second wiring members extend in a second direction. Each of the second wiring members is segmented into a plurality of second wiring portions. The light emitting elements are disposed along the second direction. A first electrode of the light emitting element is connected to a corresponding one of the first wiring members. A second electrode of the light emitting element has a first connection part and a second connection part that is linked to the first connection part. The first connection part and the second connection part are connected to a corresponding one of the second wiring members and bridge at least two of the segmented second wiring portions in the second direction.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: April 9, 2019
    Assignee: NICHIA CORPORATION
    Inventor: Takuya Nakabayashi
  • Patent number: 10257899
    Abstract: An automatically reconfiguring light-emitting circuit includes a first and second block of electric lights, a switching mechanism, the switching mechanism having (i) a first state in which the switching mechanism electrically connects the first block of electric lights in parallel with the second block of electric lights and (ii) a second state in which the switching mechanism electrically connects the first block of electric lights in series with the second block of electric lights, a current regulator that generates a current control signal in response to a current in the first group of lights and second group of lights, and a controller electrically connected to the switching mechanism, the controller configured to switch the switching mechanism between the first state and the second state based on the current control signal.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: April 9, 2019
    Assignee: LiteIdeas, LLC
    Inventor: Paul D Rucker