Abstract: Memory devices employ circuitry that may be used to adjust the output impedance. Embodiments describe herein relate to fuse-based adjustment circuitry that may be used to assist output impedance compensation such as ZQ calibration, and facilitate reduction in the dimensions and/or power consumption of the memory device.

Abstract: Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter, and configured for driving the input/output pad to a voltage level based on the data signal and the output enable signal.

Abstract: System and method for providing at least an output current to one or more light emitting diodes. The system includes a control component configured to receive at least a demagnetization signal, a sensed signal and a reference signal and to generate a control signal based on at least information associated with the demagnetization signal, the sensed signal and the reference signal, and a logic and driving component configured to receive at least the control signal and output a drive signal to a switch based on at least information associated with the control signal. The switch is connected to a first diode terminal of a diode and a first inductor terminal of an inductor. The diode further includes a second diode terminal, and the inductor further includes a second inductor terminal.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: A temperature-dependent current generator includes a first transistor connected between first and second nodes and providing a first voltage potential at the second node that decreases first order linearly when ambient temperature increases. The generator further includes an operational amplifier having first and second input terminals and an output terminal. The first input terminal is coupled to a second voltage potential that is first order independent of the ambient temperature. The second input terminal is coupled to a third node. The generator further includes a second transistor with gate, source, and drain terminals. The gate terminal is coupled to the output terminal of the operational amplifier. One of the source and drain terminals is coupled to the third node. The generator further includes a resistor coupled between the second and the third nodes. A resistance value of the resistor is first order independent of the ambient temperature.

Abstract: Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.

Abstract: An apparatus for performing quantum computing includes multiple qubits, each of at least a subset of the qubits comprising a loop formed of a Dirac or Weyl semimetal and having at least two stable quantum states. The apparatus further includes at least one terahertz cavity coupled with the qubits, the terahertz cavity being configured to detect the quantum states of the qubits. Each of at least the subset of qubits is configured to receive a circularly polarized radiation source. The radiation source is adapted to excite a chiral current in each of at least the subset of qubits, the quantum states of the plurality of qubits being a function of the chiral current.

Abstract: Enhancements to ornamental or holiday lighting are disclosed including remote control ornamental illumination with color pallet control whereby a user can vary the color/intensity/appearance of an individual bulb or entire light string by selecting the electronic address of the bulb and selecting its attribute. Further disclosures include: motion responsive lights which respond to sensed movement, gesture controlled lights, adjustable white color/white led sets, connectable multi-function lights, controller to sequence lights to music or other input source, rotating projection led light/tree top/table top unit, and remote controlled sequencing icicle lights and ornament lighting system.

Abstract: Devices and methods for reconfiguring a programmable fabric include identifying resources in a programmable fabric of the programmable device as belonging to a partition. Reconfiguring the programmable fabric also includes creating a mask for the partition that indicates that the identified resources belong to the partition. Reconfiguring the partition also includes reconfiguring resources, via a configuration controller, in programmable fabric associated with the partition using the mask without changing resources associated with other partitions in the programmable fabric.

Abstract: The embodiments herein describe technologies of an amplifier circuit that is designed for wideband communication with superconductive components in cryogenic applications, including Josephson Junction integrated circuits, operating in a cryogenic temperature domain (e.g., 4K). The amplifier circuit operates in a temperature domain (e.g., 77K) that is higher than the cryogenic temperature domain of the superconductive components.

Abstract: A light-emitting diode (LED) luminaire comprising a normally operated portion and an emergency operated portion is used to replace a luminaire operated only in a normal mode with alternate-current (AC) mains. The normally operated portion comprises LED arrays and a power supply whereas the emergency operated portion comprises a rechargeable battery, a charging circuit, an LED driving circuit, a self-diagnostic circuit, and a charging detection and control circuit. According to availability of the AC mains, the LED luminaire can auto-select to work in an emergency mode when a line voltage from the AC mains is unavailable. The self-diagnostic circuit comprises multiple timers and is configured to provide multiple sequences and to auto-test battery discharging current according to the multiple sequences. During an auto-test period, a terminal voltage on the rechargeable battery and an LED forward voltage across the LED arrays are examined with test results displayed in a status indicator.

Abstract: A light-emitting diode (LED) luminaire comprises a rechargeable battery, LED array(s), at least two drivers, a battery charging circuit, and a luminaire control circuit. The LED luminaire may be used to replace a fluorescent or a conventional LED lamp connected to AC mains to operate in both a normal mode and an emergency mode. The at least two drivers comprise an LED driving circuit and a power supply unit respectively configured to drive the LED arrays when AC mains are unavailable and available. The luminaire control circuit comprises a first switch circuit and a second switch circuit respectively configured to manage discharging and charging of the rechargeable battery. The luminaire control circuit further comprises a switchover circuit configured to manage an LED driving current from either the LED driving circuit or the power supply unit to drive the LED arrays without crosstalk.

Abstract: In an embodiment of the invention, an apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; a field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA; wherein the apparatus triggers a switch of an FPGA image in the FPGA to another FPGA image. In another embodiment of the invention, a method comprises: triggering, by an apparatus, a switch of an FPGA image in a field programmable gate array (FPGA) to another FPGA image; herein the apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; the field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA.

Abstract: A PUF device and a method of outputting a random sequence are disclosed. The PUF device includes: at least one processing unit and at least one PUF unit, and a first PUF unit of the at least one PUF unit includes a first MOS transistor and a second MOS transistor, two sources of the two MOS transistors are connected to a same input voltage; two gates of the two MOS transistors are floating; and two drains of the two MOS transistors are respectively connected with a first processing unit, and the first processing unit is configured to: output a first random value corresponding to the first PUF unit according to a difference between two results output by the two drains of the two MOS transistors, when the input voltage is greater than or equal to a preset voltage.

Abstract: An organic light-emitting diode comprising an organic layer sequence, a radiation exit area and an encapsulation. The organic layer sequence comprises at least one radiation-emitting region which generates electromagnetic radiation in the spectral range from infrared radiation to UV radiation during operation. The radiation exit area is structured, so that the electromagnetic radiation has a directional emission profile. The encapsulation forms a seal of the organic layer sequence against environmental influences.

Abstract: Hierarchical partial reconfiguration for integrated circuits includes converting, using computer hardware, a first partial reconfiguration module of a circuit design into a first partial reconfiguration container, wherein the circuit design is placed and routed, loading, using the computer hardware, a first netlist into the first partial reconfiguration container, wherein the first netlist includes a first plurality of partial reconfiguration modules that are initially empty, and including, using the computer hardware, a further netlist within each of the first plurality of partial reconfiguration modules. Using the computer hardware, the first partial reconfiguration container is implemented with the first plurality of partial reconfiguration modules being implemented within the first partial reconfiguration container.

Abstract: System and method for providing at least an output current to one or more light emitting diodes. The system includes a control component configured to receive at least a demagnetization signal, a sensed signal and a reference signal and to generate a control signal based on at least information associated with the demagnetization signal, the sensed signal and the reference signal, and a logic and driving component configured to receive at least the control signal and output a drive signal to a switch based on at least information associated with the control signal. The switch is connected to a first diode terminal of a diode and a first inductor terminal of an inductor. The diode further includes a second diode terminal, and the inductor further includes a second inductor terminal.

Abstract: An asynchronous circuit and methods for requesting that an action is triggered. The circuit performs the following steps: 1) receive a plurality of input signals, the input signals each having a first transition between states at a different time, 2) select one of the input signals based on the time of its first transition compared to the time of the first transition of the other input signals, 3) provide a request to an action block to: i) trigger the action in response to receiving the request, and ii) to provide an acknowledgement upon completion of the action, wherein the request and the action are dependent on the input signal that was selected, 4) receive the acknowledgement from the action block, and 5) initiate steps 1) to 4) for a second transition of the input signals after the plurality of input signals have undergone their first transitions.

Abstract: A logic element includes a logic block, a clock generator, a clock assigner and at least one sampling element. The logic block implements a logic function on input data to obtain a plurality output data signals. The output data signals are sampled by respective clock signals. The clock generator generates phase-shifted clock signals from a reference clock signal. The clock assigner assigns differing ones of the phase-shifted clock signals to respective output data signals. The sampling element(s) sample the output data signals in accordance with the respective assigned phase-shifted clock signals.

Abstract: An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration.