Abstract: The present invention provides a disk detection method and apparatus. The method includes: collecting a set of N pieces of real-time data that are in a one-to-one correspondence with N input/output I/O-related counters of a disk, where the N I/O-related counters include an I/O response time of the disk and a counter affecting the I/O response time; the I/O response time is a time between delivery of an operation request by an application and reception of a response of the disk to the request; determining, according to the N pieces of real-time data, whether the I/O response time is abnormal; and outputting a detection result if the I/O response time is abnormal, where the detection result is used to represent that the I/O response time is abnormal.

Abstract: A data storage device includes a controller including a descriptor generation unit suitable for generating a descriptor and a memory controller suitable for generating a command based on the descriptor; and a nonvolatile memory device including a cell region, and suitable for reading first data from the cell region and buffering the first data in response to a first read command transmitted from the memory controller and outputting the first data to the controller in response to a first cache output command transmitted from the memory controller. The descriptor generation unit transmits an interrupt descriptor to the memory controller. The memory controller generates an interrupt to the descriptor generation unit based on the interrupt descriptor, and transmits the first cache output command to the nonvolatile memory device according to an instruction of the descriptor generation unit for the interrupt.

Abstract: Systems, methods, and/or devices are used to store metadata in a storage system. In one aspect, a first user space module sends a logical memory request to a memory management module of a kernel space module. The logical memory request includes data and metadata. A second user space module obtains the metadata of the logical memory request. A storage engine of the second user space module determines, in accordance with the obtained metadata, a location in non-volatile memory for the data. A second user space module generates a physical memory request including an indication of the non-volatile memory for the data. The second user space module transmits the physical memory request to the kernel space memory management module.

Abstract: A data storage device includes a nonvolatile memory device; and a controller including a descriptor generation unit, a memory controller and a buffer unit. The descriptor generation unit: transmits a first read descriptor for first data, to the memory controller, queues a first cache output descriptor for the first data, and transmits the first cache output descriptor to the memory controller by referring to a state of clusters included in the buffer unit. The memory controller transmits a first read command to the nonvolatile memory device based on the first read descriptor, and transmits a first cache output command to the nonvolatile memory device based on the first cache output descriptor.

Abstract: A prefetcher maintains the state of stored prefetch information, such as a prefetch confidence level, when a prefetch would cross a memory page boundary. The maintained prefetch information can be used both to identify whether the stride pattern for a particular sequence of demand requests persists after the memory page boundary has been crossed, and to continue to issue prefetch requests according to the identified pattern. The prefetcher therefore does not have re-identify a stride pattern each time a page boundary is crossed by a sequence of demand requests, thereby improving the efficiency and accuracy of the prefetcher.

Abstract: Methods and systems which, for example, reduce energy usage in cache memories are described. Cache location information regarding the location of cachelines which are stored in a tracked portion of a memory hierarchy is stored in a cache location table. Address tags are stored with corresponding location information in the cache location table to associate the address tag with the cacheline and its cache location information. When a cacheline is moved to a new location in the memory hierarchy, the cache location table is updated so that the cache location information indicates where the cacheline is located within the memory hierarchy.

Abstract: Aspects include a computer-implemented method that includes receiving an instruction at a processor, the instruction associated with a memory block having an address, and accessing a state indicator by the processor. The state indicator indicates whether the memory block is in a pre-defined state, and the state indicator is accessible by the processor independent of the memory block. The method also includes, based on the state indicator indicating that the memory block is in the pre-defined state, inspecting a subset of data values in the memory block, and identifying the pre-defined state of the memory block based on the subset of data values.

Abstract: Aspects include a computer-implemented method includes receiving an instruction at a processor, the instruction associated with a memory block having an address, and accessing a state indicator by the processor. The state indicator indicates whether the memory block is in a pre-defined state, and the state indicator is accessible by the processor independent of the memory block. The method also includes, based on the state indicator indicating that the memory block is in the pre-defined state, inspecting a subset of data values in the memory block, and identifying the pre-defined state of the memory block based on the subset of data values.

Abstract: A distributed storage device includes a control unit and a plurality of storage units. The control unit has a network interface, to receive a work instruction sent by at least one user end via a network. Each storage unit supports a non-volatile memory host controller interface (NVMHCI) specification and includes at least one non-volatile memory and a storage controller. The storage controller is capable of performing an operation on the at least one non-volatile memory according to the work instruction, to share operation resources of the control unit. The operation may be thin provisioning that establishes a physical volume and a logical volume for the storage unit.

Abstract: Methods and systems for in direct data access in, e.g., multi-level cache memory systems are described. A cache memory system includes a cache location buffer configured to store cache location entries, wherein each cache location entry includes an address tag and a cache location table which are associated with a respective cacheline stored in a cache memory. The system also includes a first cache memory configured to store cachelines, each cacheline having data and an identity of a corresponding cache location entry in the cache location buffer, and a second cache memory configured to store cachelines, each cacheline having data and an identity of a corresponding cache location entry in the cache location buffer. Responsive to a memory access request for a cacheline, the cache location buffer generates access information using one of the cache location tables which enables access to the cacheline without performing a tag comparison at the one of the first and second cache memories.

Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.

Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.

Abstract: According to embodiments described herein, the hierarchical complexity for coherence protocols associated with clustered cache architectures can be encapsulated in a simple function, i.e., that of determining when a data block is shared entirely within a cluster (i.e., a sub-tree of the hierarchy) and is private from the outside. This allows embodiments to eliminate complex recursive coherence operations that span the hierarchy and instead employ simple coherence mechanisms such as self-invalidation and write-through but which are restricted to operate where a data block is shared. Thus embodiments recognize that, in the context of clustered cache hierarchies, data can be shared entirely within one cluster but can be private (unshared) to this cluster when viewed from the perspective of other clusters. This characteristic of the data can be determined and then used to locally simplify coherence protocols.

Abstract: A memory controller includes: a memory that holds a physical block counter including the number of erase times, a logical block counter including the number of write times, and a logical-physical conversion table; and a control unit that writes data to any physical block address. When the control unit receives a writing data instruction, the control unit updates the number of write times corresponding to the write destination logical block address, if the number of write times corresponding to the write destination logical block address is large, the control unit allocates to the write destination logical block address a physical block address with the number of erase times which is small among spare blocks not allocated to the logical block addresses in the logical-physical conversion table, updates the number of erase times corresponding to the allocated physical block address, and updates the logical-physical conversion table.

Abstract: Aspects include a computer-implemented method for receiving an instruction at a processor, the instruction associated with a memory block having an address. A clear indicator that indicates whether the memory block is in a cleared state is assessed by the processor. The cleared state is a state of the memory block in which the memory block does not have any data stored therein. The method also includes determining based on the clear indicator whether the memory block is in the cleared state.

Abstract: Aspects include a computer-implemented method for receiving an instruction at a processor, the instruction associated with a memory block having an address. A clear indicator that indicates whether the memory block is in a cleared state is assessed by the processor. The cleared state is a state of the memory block in which the memory block does not have any data stored therein. The method also includes determining based on the clear indicator whether the memory block is in the cleared state.

Abstract: In one embodiment, a computer-implemented method includes capturing a consistent state of data blocks in a namespace cache of a deduplicating storage system. The data blocks contains data for a file system namespace organized in a hierarchical data structure. Each leaf page of the hierarchical data structure contains one or more data blocks. The method further includes determining, for each data block, whether the data block has been written to base on the captured consistent state. For at least one of the written data blocks in the namespace cache, the method includes searching, in the hierarchical data structure, adjacent data blocks to find in the namespace cache one or more data blocks that have also been written to, and upon finding the one or more adjacent written data blocks, flushing the written data block and the found one or more adjacent written data blocks together into a common storage unit.

Abstract: A semiconductor device may include a first address cache configured to store a physical address of a semiconductor memory device and a write count associated with the physical address, an address monitor configured to update the physical address and the write count in the first address cache based on a received write request, and an arbiter configured to store a write address and write data associated with the write request in a write cache in response to a command from the address monitor, wherein the command generated by the address monitor is based on whether an update is made to the physical address and the write count in first address cache.

Abstract: A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the one or more SSDs and creating a NVMe command structure for each sub-command.

Abstract: Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor at a first access level and at least one guest operating system at a second access level. The managing includes: at the second access level, translating from virtual addresses to intermediate physical; at the second access level, determining reuse information for ranges of virtual addresses based on estimated reuse of data stored within a virtual address space; at the first access level, translating from the intermediate physical addresses to physical addresses; at the first access level, determining reuse information for ranges of intermediate physical addresses based on estimated reuse of data stored within an intermediate physical address space; and processing reuse information determined at different access levels to store cache lines in selected portions of a first cache.