Patents Examined by James J Thomas
  • Patent number: 9898407
    Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ekaterina M Ambroladze, Deanna P Berger, Michael F Fee, Arthur J O'Neill, Robert J Sonnelitter, III
  • Patent number: 9886382
    Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ekaterina M Ambroladze, Deanna P Berger, Michael F Fee, Arthur J O'Neill, Robert J Sonnelitter, III
  • Patent number: 9875195
    Abstract: A system and method are disclosed for managing memory interleaving patterns in a system with multiple memory devices. The system includes a processor configured to access multiple memory devices. The method includes receiving a first plurality of data blocks, and then storing the first plurality of data blocks using an interleaving pattern in which successive blocks of the first plurality of data blocks are stored in each of the memory devices. The method also includes receiving a second plurality of data blocks, and then storing successive blocks of the second plurality of data blocks in a first memory device of the multiple memory devices.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: January 23, 2018
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Nuwan S. Jayasena, Lisa R. Hsu, James M. O'Connor
  • Patent number: 9812186
    Abstract: A first level buffer chip gates a target second level buffer chip according to a preset mapping relationship, a first chip select signal, and a first higher-order address signal, and forwards a memory access instruction and a lower-order address signal received from a memory controller to the target second level buffer chip. The target second level buffer chip determines a target memory module according to a second chip select signal and a delayed address signal obtained by delay processing on a second higher-order address signal, determines a target memory chip according to the lower-order address signal, acquires target data from the target memory chip according to the memory access instruction, and returns the target data to the memory controller. A cascading manner of a system memory is changed to a tree-like topological form, which avoids a protocol conversion problem and reduces the memory access time.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: November 7, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yuan Ruan, Mingyu Chen
  • Patent number: 9734059
    Abstract: A method of way prediction for a data cache having a plurality of ways is provided. Responsive to an instruction to access a stack data block, the method accesses identifying information associated with a plurality of most recently accessed ways of a data cache to determine whether the stack data block resides in one of the plurality of most recently accessed ways of the data cache, wherein the identifying information is accessed from a subset of an array of identifying information corresponding to the plurality of most recently accessed ways; and when the stack data block resides in one of the plurality of most recently accessed ways of the data cache, the method accesses the stack data block from the data cache.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: August 15, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lena E. Olson, Yasuko Eckert, Vilas K. Sridharan, James M. O'Connor, Mark D. Hill, Srilatha Manne
  • Patent number: 9652151
    Abstract: A storage controller receives hints provided by one or more applications over a period of time, wherein the hints are used by the storage controller for organizing data in storage managed by the storage controller. Data on conflicts caused by the provided hints are collected over the period of time. Based on the collected data on the conflicts, one or more conflict avoidance rules are executed to reduce possibility of future conflicts.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: May 16, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence Y. Chiu, Yang Liu, Mei Mei, Sangeetha Seshadri
  • Patent number: 9575905
    Abstract: A storage controller is provided. The storage controller includes a memory storing an indication of a current owner, a previous owner, and a preferred owner for each of one or more logical volumes. The storage controller is configured to write protect the logical volumes where the current owner and the preferred owner is the storage controller and the previous owner of the logical volumes was a different storage controller. For the logical volumes where the storage controller is the preferred but not the current owner, the storage controller is set as the current and preferred owner of the logical volumes that the different storage controller was the current but not the preferred owner for, storage controller is set as the previous owner of the logical volumes that the storage controller is the current and preferred owner of, and allowing read and write access to the one or more logical volumes.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: February 21, 2017
    Assignee: Seagate Technology LLC
    Inventor: Ritvik Viswanatha
  • Patent number: 9558115
    Abstract: A method includes receiving an atomic operation for execution, wherein the execution of the atomic operation is to access a data container stored in more than one data store device of a plurality of data store devices in a distributed storage system. The method includes executing, in response to receiving the atomic operation, a write-back cache operation for the data container to preclude access of the data container by a different operation prior to completion of the atomic operation. The method also includes executing the atomic operation, wherein executing the atomic operation comprises accessing the data container stored in the more than one data store device of the distributed storage system.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: January 31, 2017
    Assignee: NETAPP, INC.
    Inventor: Richard Parvin Jernigan, IV
  • Patent number: 9471228
    Abstract: Aspects of the disclosure provide for caching policies for solid state drives. A method of the disclosure includes receiving a request to perform a write operation of a first size; determining, by a processing device, a threshold of input/output I/O size in view of an average bandwidth of a solid state drive (SSD) and information related to I/O operations performed by at least one of the SSD or a hard disk drive (HDD); comparing the first size with the threshold of I/O size; and determining, by the processing device, whether the write operation is to be performed on the SSD or on the HDD in view of the comparison.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: October 18, 2016
    Assignee: Red Hat, Inc.
    Inventor: Henri van Riel
  • Patent number: 9389807
    Abstract: A storage controller receives hints provided by one or more applications over a period of time, wherein the hints are used by the storage controller for organizing data in storage managed by the storage controller. Data on conflicts caused by the provided hints are collected over the period of time. Based on the collected data on the conflicts, one or more conflict avoidance rules are executed to reduce possibility of future conflicts.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: July 12, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence Y. Chiu, Yang Liu, Mei Mei, Sangeetha Seshadri
  • Patent number: 9378145
    Abstract: A method for a pair of redundant storage controllers to ensure reliable cached write data transfers to storage device logical volumes is provided. The method includes maintaining metadata including a first number identifying which controller currently owns the volume, a second number identifying which controller previously owned the volume, a third number identifying which controller is a preferred owner of the volume, and an indication if the volume is write protected. The method also includes determining if all volumes currently owned by the controller are write protected. If all volumes currently owned by the controller are write protected, then the method includes verifying that the second controller is working and transferring cache data from the second controller to the first controller. If all volumes currently owned by the first controller are not write protected, then the method includes updating the second number and placing all volumes online.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: June 28, 2016
    Assignee: Dot Hill Systems Corporation
    Inventor: Ritvik Viswanatha