Abstract: The present invention provides a unified layer for Plug and Play (PnP) components and power management components while relieving device drivers from system-level complexities associated with implementing PnP and/or power management functionality. The layer operates at a level between low-level device drivers and more complex operating system tasks. The subject invention simplifies designing device drivers having proper power management support by creating an infrastructure that allows a device driver to operate within a driver framework or model and without having to process Plug-and-Play or Power Management I/O Request Packets (IRPs) directly.

Abstract: A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e.g., from internal device logic) is output from the data I/O device to the at least one port.

Abstract: A computer apparatus provides control for automatically switching the apparatus between various operating modes requiring varying levels of power consumption. An embedded controller determines whether or not the computer apparatus is in motion (vibration, acceleration, rotation, etc.) on the basis of acceleration information obtained through an accelerometer provided in the computer apparatus. If the computer apparatus is in motion, the embedded controller provides control so as to prevent switching between system operating modes in order to protect certain components of the apparatus from damage which might be caused by switching operating modes while in motion.

Abstract: A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memory bus and provide scrambled data for use in the periodic recalibration.

Abstract: A power supply subsystem for providing electrical power to a local area network node over communication cabling, the power supply subsystem containing: a power management and control unit; programmable current limiting circuitry responsive to the power management and control unit to provide a programmable current limited output; voltage measurement means; and at least one of a combiner and a power supply interface operative to couple the programmable current limited output to the communication cabling. The power management and control unit is operative to: measure, utilizing the voltage measuring means at a plurality of pre-determined intervals, a voltage developed in accordance with the coupled programmable current limited output; and determine, as a consequence of the measured voltage whether characteristics of the node allow it to receive power over the communication cabling.

Abstract: In a backup system 310, 340, 350, or 360, a controller 300 controls operation of a multi-source audio apparatus MMSA. An operation status holder 310 holds operation status information Dbk of the multi-source audio apparatus MMSA. A non-volatile memory 340 stores the operation status information Dbk. A capacitor 360 as a power storage means stores part Pt of operating power. An operating power detector 350 (Sps) detects whether or not the operating power is being supplied. An operation status information write device 310 selectively writes the operation status information Dbk into the non-volatile memory 34 depending on whether or not the operating power is being supplied.

Abstract: A memory device has a plurality of memory blocks utilized to store data. One of the blocks is used as a hidden memory block to store an operating system program, instead of data. The hidden memory block is designated as a bad block so that data will not be written into the hidden memory block, but a tag associated with the hidden memory block identifies that the hidden memory block contains the operating system program.

Abstract: Systems and methods are disclosed for removing a power supply from a host unit running a computer program, without losing data or causing a cold boot. The present invention employs a retaining assembly for the power supply that delays removal of the power supply until shutting down of the computer program of the host unit. The system may further comprise a logic unit that estimates the period from initiating a power off for the unit, up to an actual shut down of the computer program.

Abstract: A microcontroller integrated circuit with a clock controller and a processor automatically switches the source of the clock signal that clocks the processor from a failed fast external precision oscillator to a slow internal backup oscillator, then enables a fast internal precision oscillator, and finally switches to the fast internal precision oscillator. A failure detection circuit within the clock controller detects a failure of the external precision oscillator and sends an associated interrupt signal to the processor. The clock controller decouples the external oscillator from the processor and couples the backup oscillator to the processor. The microcontroller integrated circuit then enables the fast internal precision oscillator, decouples the backup oscillator, and couples the fast internal precision oscillator to the processor.

Abstract: Methods and circuits to define a thermal operating mode for a integrated device by defining an operating voltage and a frequency range.

Abstract: An optical network terminal includes a sleep logic circuit that assumes responsibility for monitoring off-hook transitions after the AC main power supply has failed for a predetermined period of time. The sleep logic circuit is very low power and, as a result, allows the optical network terminal to remain active and provide lifeline support for a much greater period of time.

Abstract: An interrupt timer module comprises a prescale counter (PSC) incremented by a real-time interrupt clock signal (RTICLK), a prescale compare value register (CVR) storing a configurable value (PCV), a comparator comparing the current count of the prescale counter (PSC) with the stored configurable value (PCV), a free running counter (FRC) incremented by a match from the comparator, and a plurality of interrupt generation units (IGU0, IGU1, IGU2) Each interrupt generation unit (IGU0, IGU1, IGU2) comprises a compare value register (CVR0, CVR1, CVR2) storing a compare value and a comparator comparing the compare value from the respective compare value register with the current count of the free running counter providing one or both of an interrupt signal (INT0, INT1, INT2) and a direct memory request signal (DMAREQ0, DMAREQ1, DMAREQ2) upon a match.

Abstract: A circuit for protecting a motherboard if a component is not connected properly to its power source, a startup circuit (50) connected to a switch, and a monitoring circuit (70) monitoring the status of the component. The startup circuit provides a control signal to a power supply (10) via the switch for controlling the power supply providing power to the motherboard. The monitoring circuit outputs a monitoring signal to the switch to control the switch to be on or off, so as to control the transfer of the control signal.

Abstract: A circuit according to an embodiment of the present invention comprises a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a PLL circuit which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at an end point of the first clock distribution network, to a start point of the first clock distribution network, and a PLL circuit which provides a second output signal obtained by making the phase of the reference clock signal coincident with a phase of a clock signal at an end point of the second clock distribution network, to a start point of the second clock distribution network.

Abstract: A system is provided for configuring a configurable device. The system includes an internal bus in communication with registers and to a configuration circuit. The configuration circuit may include its own registers. The configuration circuit tests a content of at least one of the registers and performs an operation in accordance with the result of the test.

Abstract: Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.

Abstract: A power regulating system and method are provided for regulating power in a portable computing device. The portable computing device includes microprocessing and radio communication capabilities. The power regulating system utilizes a number of power states to regulate the device's internal power source voltage. The power regulating system operates to selectively control and regulate the device's internal power consumption based on the power state of the device, and thereby extends the useful life of the device by prolonging the battery life of the device.

Abstract: The present invention is directed to a method and apparatus of automatic power management control for a Serial ATA device directly attached to a SAS/SATA host controller. In an exemplary aspect of the present invention, it is determined whether a Serial ATA device is directly attached to a SAS/SATA host controller without using a SAS expander. When it is determined that the Serial ATA device is directly attached to the SAS/SATA host controller, an idle or active condition of a Serial ATA interface including the Serial ATA device and the SAS/SATA host controller is automatically detected. When the Serial ATA interface is in an idle condition, idle time of the Serial ATA interface is measured using a power down counter whose frequency is determined by a programmable register based on an input clock. When a power down counter value is equal to a first value, a request for a Partial power state is asserted, and Serial ATA interface is put into a Partial power state.

Abstract: An image forming device having a communication unit includes a system control unit which controls the entire image forming apparatus, the system control unit having a CPU that is set in one of a normal mode, a power-saving mode and a sleep mode by controlling a power supply unit. A real-time clock keeps track of hours, minutes and seconds of a current time and outputs a signal indicating the current time. A register stores a return time that indicates a time the CPU is to be switched from one of the power-saving mode and the sleep mode to the normal mode. A comparator compares the current time of the clock with the return time of the register, and outputs, when a match occurs, a control signal to the CPU so that the CPU is switched to the normal mode.

Abstract: A data transfer method which is capable of transferring a predetermined amount of data in one transaction at only one time, and preventing the number of ports of a master chip and the number of signal lines connected between the master chip and slave chips from being increased. A single master chip and a plurality of slave chips which receive data transferred from the master chip are connected by a ring-like path. Data is transferred from the master chip to the slave chips via the ring-like path.