Abstract: A technique for compensating for duty cycle distortion in an output data signal generated by a synchronous dynamic random access memory device (SDRAM) is provided. The output latch of the SDRAM is driven by an output clock signal generated by a delay lock loop (DLL). The output clock signal is phase-shifted relative to a reference clock signal received by the DLL such that the data removed from the output latch is synchronous with the reference clock signal. Further the duty cycle of the output clock signal is adjusted in a phase inverse relationship to the duty cycle distortion introduced by the output latch. As a result, the output data signal has reduced duty cycle distortion.

Abstract: A printer changes a setup menu in such a way as to enable a user to select an automatic mode for automatically setting a switching time for switching to a power saving mode in accordance with information concerning execution frequency of a printing process, when a prescribed discrepancy occurs between a prescribed switching time and actual printing process execution status.

Abstract: A method and apparatus to decrease the boot time and the hibernate awaken time of a computer system is presented. Static and dynamic configuration data is stored in flash memory. The size of flash memory is selected so that the initialization time of the configuration data stored in the flash memory is approximately equal to the spin-up time of the disk drive where the operating system is stored. During power down or entry into a hibernate mode, the computer system determines the static and dynamic configuration data to be stored in flash memory based on a history of prior uses. Data is also stored in the flash memory during system operation to reduce the number of times the disk drive is spun up. When the computer system is powered up or awakened from hibernation, the configuration data in flash memory is initialized while the disk drive is spinning up.

Abstract: An apparatus and method for initializing a coprocessor for use in system comprised of a main processor and coprocessor. The apparatus can be provided with fewer required memory components, such as a NOR flash memory, by enabling a coprocessor to perform a booting function upon receiving a control signal from the main processor.

Abstract: A method and apparatus are provided for controlling the power consumption of a semiconductor device such as a CPU or other form of processor that is operable to process a sequence of instructions. The device includes a monitor for checking the power consumption of the device, in order to detect any significant change in power consumption (which can cause problems for the power supply circuitry). In order to mitigate such change, one or more dummy instructions are inserted into the sequence of instructions. The dummy instructions do not affect the logical processing, but are selected in order to limit the change in power consumption. Thus if the change in power consumption represents an increase, then dummy instructions are selected that do not require much current. Conversely, if the change in power consumption represents a decrease, then dummy instructions are selected that draw a relatively large amount of current.

Abstract: A system and method for coordinating synchronizer controllers disposed in different clock domains, e.g., a core clock domain and a bus clock domain, wherein a clock synchronizer arrangement is employed for effectuating data transfer across a clock boundary therebetween. A bus clock synchronizer controller operable in the bus clock domain includes circuitry for generating a set of inter-controller clock relationship control signals, which are provided to a core clock synchronizer controller. Responsive to the inter-controller clock relationship control signals, circuitry in the core clock synchronizer controller is operable to synchronize the core clock signal's cycle and sequence information relative to the bus clock signal.

Abstract: The invention consists of a boot loader for a device, comprising an IP stack supporting Internet protocols, and a scripting engine to run a default script. The IP stack includes address discovery service (for example, BOOTP and DHCP), a URI to IP address translator (for example, DNS), and a protocol for file transfer over the Internet (for example, HTTP, FTP and/or TFTP). On start-up of the device, the boot loader runs the default script to initialize the device and verify the integrity of any data and operating systems in memory on the device.

Abstract: An instruction conversion apparatus for optimizing an instruction program formed of a plurality of instructions to be suitable for execution by a microprocessor that has a plurality of hard ware resources. The apparatus includes a power control information analysis unit for detecting a power controllable hardware resource that does not operate for a certain specific instruction region in the instruction program while the microprocessor is at work, and a power control instruction providing unit for providing the instruction program with an instruction regarding the power control based on the result of the detection made by the power control information analysis unit.

Abstract: A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.

Abstract: A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the technology mapping, routing, and period following routing of the programmable logic device.

Abstract: The invention describes a system and method for arranging to provide power to a power monitor device. The disclosure describes the system and method receiving a request for power for at least one device specified by a power monitor device. The disclosure describes receiving at least one proposal from an entity desiring to supply power according to the request for power. A best proposal of the at least one proposal is determined. And the system and method command the power monitor device to supply power in accordance with the best proposal.

Abstract: A method for processing data is provided that includes receiving a clock signal at a source driver and communicating the clock signal to a plurality of destination receivers. The clock signal may be received at the destination receivers during a substantially equivalent time interval, the plurality of destination receivers being five.

Abstract: An information processing system is operated by reference clock signals supplied to a plurality of units. High frequency clock signals are generated from the reference clock signals supplied. Shift-holding of the reference clock signals is performed based on the high frequency clock signals, and shift-hold data is stored. The reference clock signals and the high frequency clock signals are synchronized based on the shift-hold data, and synchronization information is stored. Data communication is carried out between the first unit and other units, based on the synchronization information.

Abstract: An interface circuit according to one embodiment of the present invention includes a clock signal, a first phase locked loop coupled to the clock signal line and generating a reference clock signal, a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more phase shifted reference clock signals, and a data transceiver circuit coupled to receive at least one of the clock signal, the reference clock signal, or one or more of the phase shifted reference clock signals to control the flow of data between a first circuit and a second circuit. An interface circuit according to one embodiment of the invention can be used advantageously for controlling the flow of data between a CPU and an external memory.

Abstract: A message based power management approach is utilized to provide power management for a multi-processor system. A power management message is received at one processor of the multi-processor system over an input/output communication link that provides input/output access for the processors of the multi-processor system. The power management message includes a power management field encoding a power management state for processors of the multi-processor system. The processor that received the power management message over the input/output communication link sends a power management message to other processors in the multi-processor system over one or more inter-processor communication links encoding the power management state.

Abstract: A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.

Abstract: A system and method for registering and unregistering a module with a kernel includes a processing unit communicating with the kernel. A hierarchical kernel registry service communicates with the kernel and includes an identifier of the module. The processing unit causes the module to be one selected from registered with the kernel and unregistered from the kernel as a function of a hierarchical position of the identifier within the kernel registry service.

Abstract: Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.

Abstract: An interrupt signal EMG is put out to a microprocessor 10 when a thermal monitor 40 detects that a package temperature exceeds a reference. The microprocessor then increases a frequency division value N stored in a frequency division value register 31 of a clock mechanism 30. An inputted clock signal MCK is divided by N to generate a system clock signal SCK. Therefore, the frequency of system clock signal SCK decreases when N increases. Consequently, electricity consumption of each function module 20i decreases and the package temperature is reduced.

Abstract: An electric device features a two-wire interface which two-wire interface serves to feed electric power to the electric device and also to transmit a signal, with the maximum power drawn via the two-wire interface in normal operation being restricted to a predefined upper limit. The permissible maximum power consumption of the electric device is automatically and temporarily increased beyond the predefined upper limit when the electric device is switched into a special operational function mode. The length of time in which the electric device is in the special operational function mode can thus be reduced.