Abstract: A technique for compensating for duty cycle distortion in an output data signal generated by a synchronous dynamic random access memory device (SDRAM) is provided. The output latch of the SDRAM is driven by an output clock signal generated by a delay lock loop (DLL). The output clock signal is phase-shifted relative to a reference clock signal received by the DLL such that the data removed from the output latch is synchronous with the reference clock signal. Further the duty cycle of the output clock signal is adjusted in a phase inverse relationship to the duty cycle distortion introduced by the output latch. As a result, the output data signal has reduced duty cycle distortion.

Abstract: The present invention is directed to a method and apparatus of automatic power management control for Serial ATA interface. In an exemplary aspect of the present invention, an idle or active condition of Serial ATA interface is automatically detected. When Serial ATA is in an idle condition, idle time of Serial ATA interface is counted using a power down counter whose frequency is determined by a programmable register based on input clock. When a power down counter value is equal to a first value, a request for a Partial power state is asserted, and Serial ATA interface is put into a Partial power state. When a power down counter value is equal to a second value, a request for a Slumber power state is asserted, and Serial ATA interface is put into a Slumber power state.

Abstract: An electrical distribution system is disclosed that includes a gateway module (100) including logic (112) to interface to a vehicle management computer (VMC) (50) via a dual redundant standard data bus (1). The gateway module (100) has redundant microcontrollers (114, 116) operably connected to the VMC (50) for selectively controlling supply of electrical power to a plurality of separate electrical loads (120). The electrical power distribution center also has two internal serial data buses (2,3) that are of two different types. The redundant microcontrollers (114, 116) are each connected to the two internal buses (2,3). A plurality of Load Management Modules (300) is provided. Each are connected to the internal serial data buses (2,3) for receiving control commands via the gateway module (110).

Abstract: The present invention provides hardware-based synchronization within a device such as a set top box so that sets of data values can be communicated between a set of DCR registers operating at a first frequency and a set of clock register operating at a second frequency. Specifically, to communicate an initial set of data values from the set of DCR registers to the set of clock registers, a control signal is stretched and then synchronized with a clock signal having the second frequency. To communicate a current set of data values from the set of clock registers to the set of DCR registers, the control signal is synchronized with a clock signal having the first frequency. By communicating the current set of data values to the first set of registers, a hardware component (e.g., a CPU) can access the current set of data values without restriction.

Abstract: A method and apparatus to decrease the boot time and the hibernate awaken time of a computer system is presented. Static and dynamic configuration data is stored in flash memory. The size of flash memory is selected so that the initialization time of the configuration data stored in the flash memory is approximately equal to the spin-up time of the disk drive where the operating system is stored. During power down or entry into a hibernate mode, the computer system determines the static and dynamic configuration data to be stored in flash memory based on a history of prior uses. Data is also stored in the flash memory during system operation to reduce the number of times the disk drive is spun up. When the computer system is powered up or awakened from hibernation, the configuration data in flash memory is initialized while the disk drive is spinning up.

Abstract: A secure mechanism for remotely controlling the power-on state of a host computer: A microcontroller in the host computer is supplied with standby power even when system power to the host computer is turned off. The microcontroller senses the state of the host computer's RS-232 receive line so that commands may be sent to the microcontroller over an RS-232 connection to the host computer. An output of the microcontroller is logically ORed with the output of a power switch debounce circuit of the host computer. The output of the logical OR function is used to manipulate the power-on state of the host computer. The microcontroller may be programmed to respond to numerous commands.

Abstract: A method for synchronizing a data exchange between a data source and a control device is provided. A synchronization request signal is first transmitted via the bus system to the data source, which then measures a signal propagation time from the control device to the data source. In the data source, a transmission delay time is set which is dependent on the measured signal propagation time. Data which are to be transmitted are delayed by the transmission delay time. A bus system for synchronizing a data exchange is also provided. After receiving a synchronization request signal, the data source measures signal propagation times and sets a transmission delay time in a transmission delay device on the basis of the measured signal propagation times.

Abstract: The preferred embodiments of the present invention are directed to the selective phase lag and time delay of clock signals within a computer system to compensate for additional parasitic capacitance that may be added to that system because of its open architecture. More particularly, the preferred embodiments are directed to clock signal path circuits where each circuit has multiple signal paths of varying lengths. By allowing the clock signals to propagate along a particular path, phase lag or time delay is added to those clock signals. Selection of a particular path for the clock signal is made by activating electrically controlled switches which themselves are activated or deactivated by software programs that run during power-up of the computer system that determine required phase lag or time delay of those clock signals as a function of parasitic capacitance in the computer system.

Abstract: The present invention is directed to a method and apparatus of automatic power management control for Serial ATA interface. In an exemplary aspect of the present invention, an idle or active condition of a Serial ATA interface including a NCQ Serial ATA device is automatically detected. In this step, it is determined, preferably based on a value of the FPDMA (First Party Direct Memory Access) bit in a Task File Ram of the Serial ATA interface, whether the NCQ Serial ATA device is in a FPDMA Data Phase. When the NCQ Serial ATA device is in a FPDMA Data Phase, the Serial ATA interface is active (i.e., not idle). When Serial ATA is in an idle condition, idle time of Serial ATA interface is measured using a power down counter whose frequency is determined by a programmable register based on an input clock. When a power down counter value is equal to a first value, a request for a Partial power state is asserted, and Serial ATA interface is put into a Partial power state.

Abstract: An electrical power distribution system is disclosed that includes a gateway module (100) including logic (112) to interface to a vehicle management computer (VMC) (50) via a dual redundant standard data bus (1). The gateway module (100) has redundant microcontrollers (114, 116) operably connected to the VMC (50) for selectively controlling supply of electrical power to a plurality of separate electrical loads (120). A plurality of Load Management Modules (300) is provided. Each Load Management Module (300) includes a local microcontroller (310); power switching devices (320); and application specific integrated circuits ASICs (330) for interfacing the power switching devices (320) to the local microcontroller (310). Each ASIC (330) can be connected to a corresponding digital potentiometer (600) that is used to program an over current protection characteristic.

Abstract: An interface circuit according to one embodiment of the present invention includes a clock signal, a first phase locked loop coupled to the clock signal line and generating a reference clock signal, a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more phase shifted reference clock signals, and a data transceiver circuit coupled to receive at least one of the clock signal, the reference clock signal, or one or more of the phase shifted reference clock signals to control the flow of data between a first circuit and a second circuit. An interface circuit according to one embodiment of the invention can be used advantageously for controlling the flow of data between a CPU and an external memory.

Abstract: Thermal throttling control to safely throttle clocks OFF and ON in an integrated circuit. Digital thermal throttling control is provided to gradually throttle a clock's frequency from ON to OFF and from OFF to ON. The gradual throttling can minimize an instantaneous current rise that would otherwise occur with a rapid shut OFF and a rapid turn ON of a clock. Included are methods and apparatus for digital thermal throttle control in an integrated circuit.

Abstract: A watchdog timer circuit modified to operate during periods of microcomputer shut-down or sleeping, as for energy conservation purposes, controlled by an independent external rectangular-wave signal for inhibiting watchdog timer reset signal generation for the microcomputer during such shut-down periods and until a wake-up signal is generated at the end of such microcomputer sleeping, whereupon the watchdog circuit will generate a reset signal in the absence of proper microcomputer operation.

Abstract: In an electronic apparatus for realizing a desired function by combining a plurality of units, a judging part judges whether a combination of the plurality of units is to realize the desired function and a power supply control part controls a supply of power from a power source to at least one of the units of the combination used to realize the desired function based on a judgement result of the judging part.

Abstract: An information handling system that includes a processor, a memory, a program, a battery, and a module. The module receives a request for first information associated with the battery from the program, accesses the first information, converts the first information into second information, and provides the second information to the program in response to the request.

Abstract: A method for executing an agent code, wherein the agent code is saved in a read only memory, wherein an agent record containing data is saved in an erasable and programmable memory device, and wherein the method comprises the following steps: reading the agent code from the read only memory and loading it into a processing device, executing the agent code, thereby initiating reading the agent record from the erasable and programmable memory device and loading it into the processing device, and executing the agent record in the processing device.

Abstract: A technique includes receiving a first basic input/output system image to replace an existing second basic input/output system image stored in a firmware memory. The first basic input/output system image is modified by replacing a portion of the first basic input/output system image with a portion of the second basic input/output system image. The modified first basic input/output system image is written to the firmware memory to replace the second basic input/output system image.

Abstract: An apparatus comprising a circuit that may be configured to (i) change a frequency of one or more first signals in response to a second signal and (ii) generate a third signal in response to either the second signal or a predetermined time period expiring.

Abstract: A method and apparatus are disclosed for adjusting the individual data hold time of data output buffers. Clock signals for the output buffers are respectively and individually adjusted for each of the output buffers to ensure a desired timing relationship among all of the data output by the buffers.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a first clock receiver, one or more clock traces coupled to the clock generator, and clock generator coupled to the one or more clock traces. The clock generator gates clock signals to the first clock receiver in response to detecting that the clock traces have been disconnected from electrical ground.