Abstract: An adhesive silicone sheet that enroute to its complete cure is inhibited from releasing low-viscosity silicone oil, that provides excellent bond between a semiconductor chip and the corresponding chip attachment site, and that as a consequence of these features supports the fabrication of highly reliable semiconductor devices, The adhesive silicone sheet is produced by a very efficient method which yields an adhesive silicone sheet having particularly good adhesiveness. The siliocone adhesive sheet is used to produce highly reliable semiconductor devices in which the semiconductor chip has been bonded to its attachment site using the subject adhesive silicone sheet.

Abstract: In a semiconductor device including a substrate which has a primary surface, a conduction wire formed on the primary surface, a semiconductor element which has a secondary surface, a projective electrode formed on the secondary surface, an insulative resin for adhesion which is applied between the primary surface and the secondary surface and which shrinks by hardening thereof, the substrate and the semiconductor element are adhered to each other by the hardening of the insulative resin with the projective electrode and the conduction wire corresponding with each other, so that an electrical connection between the projective electrode and the conduction wire is achieved and that a residual stress is generated in the insulative resin. The residual stress has a maximum value thereof around the projective electrode.

Abstract: A method of for fabrication a metal oxide semiconductor transistor is described. A substrate with an isolation structure thereon is provided. A gate oxide layer is formed on the substrate. A polysilicon layer is formed on the gate oxide layer. The polysilicon layer is patterned to form a gate on the gate oxide layer. An offset spacer is formed on the sidewall of the gate. A source/drain extension is formed in the substrate on two sides of the gate by ion implantation. An insulating spacer is formed on the sidewall of the offset spacer. A source/drain region is formed in the substrate by ion implantation using the gate, the offset spacer and the insulating spacer as a mask. Salicide is formed on the gate and on the surface of the source/drain region. After forming the salicide, the offset spacer is removed. After removing the offset spacer, a halo doped region is formed in the substrate below the source/drain extension by ion implantation.

Abstract: A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, and employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants. Appropriate openings are formed in the field implant blocking mask so that the field implant occurs at the edges of the junctions, thus achieving low leakage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

Abstract: Various alignment targets are disclosed having improved visibility. A first embodiment includes an alignment target having a first reflective layer of a first material such as tungsten having a roughened surface; and a second layer of a second material, such as aluminum, deposited on the first layer. The surface of the second layer is roughened by conforming with the roughened surface of the first layer to provide both layers with a uniform optical layers. The edges of the second layer provides an optical signal to contrast between the two layers for alignment. A second embodiment includes an alignment target with a plurality of parallel elongated trenches; a first material fills each of the trenches; and a patterned layer of a second material is deposited on top the elongated trenches and the insulator layer.

Abstract: Lifetime of a short-channel NMOS device is increased by modifying distributions of electrically active LDD dopant at boundaries of the device's LDD regions. The LDD dopant distributions are modified by implanting counter-dopants at the boundaries of the LDD regions. Group III counter-dopants such as boron and group IV elements such as silicon alter activation properties of the LDD dopant. The dopant distributions are modified at the device's n-junctions to reduce the maximum electric field displacement at an interface defined by the device's gate and substrate. The dopant distributions can be further modified to shape the n-junctions such that hot carriers are injected away from the gate.

Abstract: This invention relates to a method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of said device, wherein at least some of the contaminate nitrogen has formed a bond with the surface of the silicon substrate in contact with the gate oxide layer in said gate region, said method comprising: contacting said gate oxide layer and contaminate nitrogen with a gas comprising ozone at a temperature of about 850° C. to about 950° C. for an effective period of time to break said bond; and removing said gate oxide layer and contaminate nitrogen from said surface of said silicon substrate.

Abstract: A semiconductor device in which a salicide structure is applied to a buried gate transistor to largely reduce a difference of level or height in a element and to reduce the resistance of a gate electrode and a source/drain structure, thus enabling reliable high speed operations while maintaining high performance. For manufacturing the semiconductor device, a silicon substrate is formed with a groove for a buried gate. A gate insulating film is formed on the bottom surface of the groove. Then, side-wall insulating films are formed on both side surfaces of the groove in a large thickness as compared with that of the gate insulating film. Next, after a gate electrode is formed from a polycrystalline silicon film, a source/drain structure is formed in the silicon substrate through the gate electrode and the side-wall insulating film. Then, a Ti film is formed and annealed to form silicide layers on the gate electrode and on the source/drain electrodes, thus completing a salicide structure.

Abstract: A method is provided for forming a split-gate flash memory cell having a sharp beak of poly which substantially improves the programming erase speed of the cell. The sharp beak is formed through an extra and judicious wet etch of the polyoxide formed after the oxidation of the first polysilicon layer. The extra oxide dip causes the polyoxide to be removed peripherally thus forming a re-entrant cavity along the edge of the floating gate. The re-entrant beak is such that it does not get damaged during the subsequent process steps and is especially suited for cell sizes smaller than 0.35 micrometers.

Abstract: A method of fabricating a semiconductor device is provided including the steps of:(a) forming one or more protrusions on a semiconductor surface,(b) forming a first O.sub.x /TEOS film on top and side surfaces of the protrusions and surface area portions of the semiconductor surface separating the protrusions from each other, if any, and(c) forming a second O.sub.3 /TEOS film on, and covering, the first film.Illustratively, the protrusions have nitride regions at their peaks. The first film can be a low pressure (e.g., 30-70 torr) O.sub.3 /TEOS film or a plasma enhanced chemical vapor deposition (PECVD) O.sub.2 /TEOS film. The second film is a high pressure (e.g., 200-600 torr) O.sub.3 /TEOS film.The high pressure O.sub.3 /TEOS film avoids all of the disadvantages of the prior art. The low pressure O.sub.3 /TEOS film or PECVD O.sub.2 /TEOS film covers the nitride region of the protrusion so that the high pressure O.sub.3 /TEOS film will continuously cover the entire structure with a uniform thickness.

Abstract: A method of manufacturing a semiconductor device is provided in which a well patterned lead line structure is obtained. In one aspect of the invention, the method comprises steps of:depositing on a semiconductor wafer a metal layer for forming lead lines at a first predetermined temperature of about 400.degree. C., say; anddepositing an anti-reflective layer on the metal layer in the following multi-deposition steps:step 1: a thin anti-reflective layer is deposited on the metal layer near the first predetermined deposition temperature;step 2: the metal layer is cooled to a second predetermined deposition temperature of about 150.degree. C., say while interrupting the deposition of the anti-reflective layer; andstep 3: the anti-reflective layer is grown to a predetermined thickness by resuming the deposition thereof at the second predetermined deposition temperature.

Abstract: The present invention provides a method and system for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects. The method and system includes implanting first low-dose arsenic into an area in the substrate, thermally diffusing the first low-dose arsenic through a portion of the substrate, implanting a second higher-dose arsenic into the area in the substrate, and diffusing the second higher-dose arsenic into the area in the substrate. Under the present invention, the combination of the first and second arsenic implants has a graded lateral profile which reduces band-to-band tunneling current and short-channel effects. The method also improves the reliability and performance of the semiconductor devices.

Abstract: A method for forming a gate dielectric having different thickness begins by providing a substrate (12). A sacrificial oxide (14) is formed overlying the substrate (12). A first portion (11) of the sacrificial oxide (14) is exposed to a carbon-containing plasma environment (20). This carbon-containing plasma environment (20) forms a carbon-containing layer (24) within the region (11). After forming this region (24), a wet etch chemistry (22) is used to remove remaining portions of the sacrificial oxide (14) without forming a layer (24) in the region (13). Furnace oxidation is then used to form regions (26a) and (26b) wherein the growth of region (26a) has been retarded by the presence of the region (24). Therefore, the regions (26a) and (26b) are differing in thickness and can be used to make different transistors having different current gains.

Abstract: A method is provided for fabricating a nonvolatile memory device having a simple stacked stricture with program gates. The method includes forming bitlines of second conductivity type along a first direction separated by a first prescribed distance in a substrate of a first conductivity type and forming first lines on the substrate along a second direction separated from one another by a second prescribed distance. The second direction is substantially perpendicular to the first direction, and the first lines include a first conductive layer on an isolating layer. A gate insulating layer is formed on the substrate and a tunneling insulating layer on the first conductive lines and a second conductive layer is formed on the entire surface. The second conductive layer, the tunneling insulating layer, and the first conductive lines are selectively removed to form second conductive lines along the first direction and program gates.

Abstract: A method for forming interconnection plugs comprising the steps of providing a substrate having a dielectric layer formed thereon, wherein an opening exposing a pad area for connection with other structures is also formed in the dielectric layer. Next, a glue layer is formed over the pad area and the dielectric sidewalls of the opening. Subsequently, plug material is deposited into the opening forming a plug layer. This is followed by etching back the plug layer to return the plug material inside the opening to a level below the height of the dielectric layer. Then, a selective etching method having a high selectivity ratio between the dielectric layer and the plug layer is used to etch the dielectric layer. Finally, the dielectric layer and the plug layer are etched to almost the same level of height.

Abstract: There is provided a semiconductor device including a semiconductor substrate, a gate electrode formed on the semiconductor substrate, a gate insulating layer sandwiched between the gate electrode and the semiconductor substrate, an interlayer insulating layer formed over the gate electrode and the semiconductor substrate, and a hydroxyl (OH) group trapper formed in the interlayer insulating layer. For instance, the hydroxyl group trapper is constituted of a nitrogen containing oxide layer. The semiconductor device is capable of preventing moisture contained in the interlayer insulating layer from penetrating the gate insulating layer and source/drain regions formed in the semiconductor substrate, resulting in that the semiconductor device can be kept away from being degraded because of hot carriers, even if the gate insulating layer were formed thinner.

Abstract: A production process for a capacitor electrode formed of a platinum metal includes producing a conductive electrode body on a substrate having a silicon-containing surface for the capacitor electrode. Platinum is deposited over the full surface, the platinum is silicized in a temperature step outside the electrode body and the platinum silicide is removed. The advantage of the invention is the avoidance of an etching process for metallic platinum.

Abstract: A method of fabricating a MOSFET includes: depositing an oxide layer on the planarized substrate; forming a silicon nitride island above a gate region in the substrate; building an oxide sidewall about the nitride island; forming a source region and a drain region in the substrate; removing the silicon nitride island, thereby leaving a void over the gate region; forming a gate dielectric over the gate region in the void; filling the void and the areas over the source region and drain region; planarizing the upper surface of the structure by chemical mechanical polishing; depositing a metal layer on the upper surface of the structure; and metallizing the structure to form electrodes in electrical contact with the source region, the gate region, and the drain region.

Abstract: A method for joining a semiconductor integrated circuit chip in a flip chip configuration, via solder balls, to solderable metal contact pads, leads or circuit lines on the circuitized surface of an organic chip carrier substrate, as well as the resulting chip package, are disclosed. The inventive method does not require the use of a solder mask, does not require the melting of the bulk of any of the solder balls and does not require the use of a fluxing agent.

Abstract: Ultra high-speed multi-level interconnect structure and fabrication process flows are disclosed for a semiconductor integrated circuit chip. The interconnect structures of this invention include a plurality of electrically conductive metallization levels. Each of the metallization levels includes a plurality of electrically conductive interconnect lines. A plurality of electrically conductive plugs make electrical connections between various metallization levels as well as between the metallization levels and the semiconductor devices fabricated on the semiconductor substrate. The invention further includes a free-space medium occupying at least a substantial fraction of the electrically insulating regions within the multi-level interconnect structure surrounding the interconnect lines and plugs. A top passivation overlayer hermetically seals the multi-level interconnect structure.