Patents Examined by James Park
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Patent number: 6121104Abstract: An integrated circuit resistor (18) has a layout in which a first parasitic capacitance (26) exists between first portions of the resistor (18) and a first integrated circuit feature (34), and a second parasitic capacitance (28) exists between second portions of the resistor and a second integrated circuit feature (32). The resistor (18) may have, for example, a zigzag or serpentine configuration, with portions of each leg of the zigzag configuration overlying the first and second integrated circuit features (34,32). The first and second integrated circuit features (34,32) are configured to produce substantially canceling charges on the first and second parasitic capacitances (26,28). The resistor may be defined by a doped semiconductor material, such as a polysilicon layer. The resistor may be used in many applications, such as a feedback resistor of an optoelectronic current-to-voltage converter (12).Type: GrantFiled: December 12, 1997Date of Patent: September 19, 2000Assignee: Texas Instruments IncorporatedInventors: Eugene G. Dierschke, Norman Culp
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Patent number: 6107182Abstract: A semiconductor device having a contact structure that can exhibit superlative step coverage without causing voids or wiring discontinuities, using aluminum or aluminum alloys as a conductive substance for via-holes. A method of fabricating the semiconductor device comprises, for at least one layer of wiring regions above the first wiring region on a semiconductor substrate, the following steps (a) to (f): (a) a step of forming a via-hole in a second interlayer dielectric formed above the first wiring region on a semiconductor substrate; (b) a degassing step for removing gaseous components included within the interlayer dielectric by a heat treatment under reduced pressure and at the substrate temperature of 300.degree. C. to 550.degree. C.; (c) a step of forming a wetting layer on the surface of the interlayer dielectric and the via-hole; (d) a step of cooling the substrate to a temperature of no more than 100.degree. C.Type: GrantFiled: September 29, 1998Date of Patent: August 22, 2000Assignee: Seiko Epson CorporationInventors: Michio Asahina, Junichi Takeuchi, Naohiro Moriya, Kazuki Matsumoto
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Patent number: 6103601Abstract: A fluorine-doped silicate glass (FSG) layer having a low dielectric constant and a method of forming such an insulating layer is described. The FSG layer is treated with a post-treatment step to make the layer resistant to moisture absorption and outgassing of fluorine atoms. In one embodiment, the post-treatment step includes forming a thin, undoped silicate glass layer on top of the FSG layer, and in another embodiment, the stability of the FSG film is increased by a post-treatment plasma step.Type: GrantFiled: June 10, 1999Date of Patent: August 15, 2000Assignee: Applied Materials, Inc.Inventors: Peter W. Lee, Stuardo Robles, Anand Gupta, Virendra V. S. Rana, Amrita Verma
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Patent number: 6100119Abstract: A thin film transistor includes an insulating substrate; a polysilicon pattern formed on the insulating substrate; a first nitride layer disposed on a channel portion of the polysilicon pattern; heavily doped semiconductor layer regions disposed in upper portions of the polysilicon pattern on sides of the first nitride layer pattern; an interlevel insulating layer disposed on the insulating substrate, the polysilicon pattern, the first nitride layer and the heavily doped semiconductor layer regions, the interlevel insulating layer having a contact hole to expose a portion of the heavily doped semiconductor layer; source and drain electrodes connected to the heavily doped semiconductor layer regions through the contact hole; and a gate electrode formed on the interlevel insulating layer disposed on the first nitride layer.Type: GrantFiled: April 9, 1998Date of Patent: August 8, 2000Assignee: LG Electronics Inc.Inventors: Jin Jang, Kyung-Ha Lee, You-Chan Chung
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Patent number: 6087261Abstract: The method of the production of a semiconductor device including the step of forming the dielectric film on or above the semiconductor substrate, placing the semiconductor substrate and the dielectric film in the atmosphere of reduced pressure and introducing into the atmosphere of reduced pressure the reaction gas for the deposition of metal or metal nitride and the oxidizing gas thereby forming the oxygen-containing conductor film formed of metal or metal nitride on the dielectric film.Type: GrantFiled: March 26, 1998Date of Patent: July 11, 2000Assignee: Fujitsu LimitedInventors: Nobuyuki Nishikawa, Toshiya Suzuki
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Patent number: 6083782Abstract: An improved GaAs MESFET includes a source contact ohmically coupled to a buffer layer or substrate to stabilize band bending at the interface of the active layer and buffer layer or substrate when an RF signal is applied to a gate electrode.Type: GrantFiled: October 21, 1999Date of Patent: July 4, 2000Assignee: Samsung Electronics Co., Ltd.Inventor: Jong Boong Lee
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Patent number: 6083801Abstract: The nickel element is provided selectively, i.e., adjacent to part of the surface of an amorphous silicon film in a long and narrow opening. The amorphous silicon film is irradiated with linear infrared light beams emitted from respective linear infrared lamps while scanned with the linear beams perpendicularly to the longitudinal direction of the opening. The longitudinal direction of the linear beams are set coincident with that of the opening. The infrared light beams are absorbed by the silicon film mainly as thermal energy, whereby a negative temperature gradient is formed in the silicon film. The temperature gradient moves as the lamps are moved for the scanning. The direction of the negative temperature gradient is set coincident with the lamp movement direction and an intended crystal growth direction, which enables crystal growth to proceed parallel with a substrate uniformly over a long distance.Type: GrantFiled: February 10, 1998Date of Patent: July 4, 2000Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hisashi Ohtani
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Patent number: 6083800Abstract: The present invention discloses a high voltage semiconductor device with high breakdown voltage without increment in area occupied an increase in the size of junction region. Each junction region includes: (i) a first impurity region of a first conductivity type of a low impurity concentration formed at a predetermined position in the semiconductor substrate, (ii) a second impurity region of a second conductivity type of a medium impurity concentration formed in the first impurity region, a part of the second impurity region being exposed to the surface of the substrate, and (iii) a third impurity region of a first conductivity type of a high impurity concentration, the third impurity region being in contact with the second impurity region, wherein a reverse bias is applied to the third impurity region.Type: GrantFiled: April 1, 1999Date of Patent: July 4, 2000Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Sang-Jun Park
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Patent number: 6043131Abstract: A method of forming a flower shaped capacitor for a DRAM over a bitline is disclosed. The method comprises the steps of: forming a first polysilicon layer over said bitline; forming a TEOS layer over said first polysilicon layer, patterning and etching an opening through said TEOS layer; depositing a second polysilicon layer; etching back said second polysilicon layer and the first polysilicon layer to form sidewall spacers in said opening; using the first polysilicon layer and sidewall spacers as a mask, etching through to said bitline and thereby removing said TEOS layer; depositing a third polysilicon layer; patterning and etching the third polysilicon layer to form a bottom storage node of the capacitor; and forming a dielectric layer and a top conductive layer over the bottom storage node.Type: GrantFiled: March 12, 1998Date of Patent: March 28, 2000Assignee: Worldwide Semiconductor Manufacturing CorporationInventor: Tzu-Chiang Yu
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Patent number: 6037234Abstract: A method of fabricating a capacitor in a DRAM. A semiconductor substrate having a metal-oxide-semiconductor is provided. Using only one photolithography process, a bottom electrode is formed. By forming a dielectric layer over the substrate, and a poly-silicon layer on the dielectric layer, a capacitor is formed.Type: GrantFiled: February 13, 1998Date of Patent: March 14, 2000Assignee: United Semiconductor Corp.Inventors: Gary Hong, Anchor Chen
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Patent number: 6017804Abstract: The invention disclosed is a method and apparatus for cleaving semiconductor material without physical contact. Tick marks are formed in a major surface of the material where cleaving is desired. A fulcrum member is moved with respect to the material until a tick mark is in alignment with the fulcrum member. A gas jet, also aligned with the fulcrum member, is applied to the surface of the material to form the cleave.Type: GrantFiled: January 9, 1998Date of Patent: January 25, 2000Assignee: Lucent Technologies Inc.Inventors: Joseph Michael Freund, George John Przybylek, Dennis Mark Romero, John William Stayt, Jr.