Abstract: A thick layer of CsI(Na) is heated to or slightly below its melting point. The CsI(Na) is held at that temperature for 7 to 10 hours and is cooled to room temperature, preferably in two steps. The resulting scintillation crystal is translucent or transparent.

Abstract: A scintillation crystal is provided for a radiation detector, which comprises a first layer of a crystal material having relatively poor mechanical properties, however having a high energy resolution; and a second layer of a crystal material having relatively good mechanical and optical properties. Both layers are arranged in sandwich form.

Abstract: A dynamic row buffer circuit is disclosed for a dynamic random access memory (DRAM) chip which enables the DRAM chip to be used for special function applications. The dynamic row buffer comprises a row buffer master register and a row buffer slave register. The row buffer master register comprises a plurality of master circuits (M1) and a plurality of slave circuits (S1). Likewise, the row buffer slave register comprises a plurality of master circuits (M2) and a plurality of slave circuits (S2). The row buffer master register is parallel load and parallel read-out with the outputs of the master register slave circuits being connected to the master circuits of the slave register. The row buffer slave register is a parallel load, serial read-out register with the output being shifted out of a secondary output port. The entire row buffer can be isolated from the memory array, and when so isolated, the memory array can be accessed through the primary input/output port in the same way as in an ordinary DRAM chip.

Abstract: A method of synchronizing the sequence by which a variety of unrelated activities are executed in a digital processor when the activities are randomly called by multiple callers includes the steps of: providing a single processor queue for holding respective pointers to each different kind of activity that the processor performs; entering the pointer of an activity in the processor queue the first time that the activity is called; providing respective activity queues for each different kind of activity that the processor performs; entering a pointer to the caller of an activity in the respective queue for the called activity each time the activity is called subsequent to its first call; repeatedly executing a single activity pointed to by one pointer in the processor queue until that activity is executed once for each of its callers, provided that if the single activity calls another activity then, executing the single activity only up to the point where the call occurs; and proceeding in the same fashion wit

Abstract: In a microprocessor including a data memory device a simple checking circuit is provided for reading out the data onto a data bus line to check whether the data must be debugged. The checking circuit reads out data stored in an accumulator, register, etc. onto the data bus line. The checking circuit allows the microprocessor to operate normally in the absence of a checking signal and respectively connects the accumulator, register, or RAM outputs to the data bus in accordance with the timing signals from the microprocessor timing signal generator in the presence of the checking signal. A program counter of the microprocessor is also inhibited from incrementing when the checking signal is present.

Abstract: An array processor includes a central vector processing unit including a plurality of vector registers and a pipe-line control arithmetic and logical operation unit (ALU) operative to execute an instruction (vector instruction) requiring vector processing, and a plurality of vector processing units including a plurality of vector registers and a pipe-line control ALU operative to execute an instruction (array instruction) requiring array processing. The central vector processing unit fetches and decodes the vector instruction or the array instruction to execute the decoded instruction, when this instruction is a vector instruction, but operates to start the vector processing units when the decoded instruction is an array instruction.

Abstract: A method and composition for providing, in situ, a polymeric membrane for isolating hazardous materials within an area such as, for example, an asbestos removal job site. The polymer is applied in liquid form to surfaces which are to be protected. Upon cure, a seamless bladder-like membrane is formed which isolates the work area and prevents the spread of airborne, or water-carried particulate. The membrane can then be peeled from the surface and compacted for disposal.

Abstract: A multi-channel electronic waveform recorder, for storing waveform data and time of occurrence information, i.e., a "time-tag", for each stored value of an input waveform, is disclosed. Specifically, each channel of the waveform recorder compares a previously stored value of a corresponding input signal to a current value, and stores the current value whenever the difference between the input signal and the previously stored value is a predetermined amount.

Abstract: A data processing system includes a cathode ray tube (CRT) display subsystem and a floppy disk subsystem. The logic of both systems are verified by generating and transferring a fixed format stream of data bits from the CRT display subsystem to the floppy disk subsystem in modified frequency modulation (MFM) mode and checking the information received by the floppy disk subsystem against the original information presented to the CRT display subsystem.The bit rate of the data stream is varied depending on the number of address locations used in the data RAM of the CRT display subsystem to store each data bit.

Abstract: An interrupt interface circuit for interrupt level sharing comprising a pulse generator having an open-collector or tri-state output connected to an external interrupt line shared by other similar circuits. An active internal interrupt signal causes the pulse generator to pulse. The external interrupt line is fed back and latched on a disabling input of the pulse generator so that any pulse on the external interrupt line prevents further pulsing. The software handler of the interrupt, upon servicing an interrupt of the interrupt level, causes the enabling of the pulse generators of that level, thereby permitting active internal interrupt signals to produce a further pulse. By this interrupt level sharing, phantom interrupts are eliminated and servicing overhead is minimized.

Abstract: A store and forward facility for use in a multiprocessing, multinode environment is disclosed wherein two fundamental processes (transfer and delivery) perform the bulk of the activities required in this facility. A transfer process permits the creation of a message by an originating applications process and transfers this message to a similar transfer process in each of the nodes to which the message is to be delivered. This message is then in turn transferred to a delivery process which maintains a work item for each message to be delivered to a destination applications process and causes a notification to be sent to that destination application process when an earliest delivery time specified in the message has been reached. The delivery process causes the destination applications process to be created if that process is not currently executing.

Abstract: Disclosed is a method and apparatus for interfacing N bit-serial communication channels to an N-bit parallel communication channel. The serial channels are interfaced simultaneously, i.e., during a single bit time, with the parallel channel by an interface unit that is shared by the serial channels. The interface unit is microprocessor based. To service all serial channels simultaneously, the microprocessor's interface program divides each bit interval into 2N time slots and allocates two time slots per bit interval to each of the N channels, one time slot for functions associted with receipt of bits from the serial channel and transmittal thereof on the parallel channel, and one time slot for functions associated with receipt of data from the parallel channel and transmittal thereof on the serial channel.

Abstract: A radiation image storage panel comprising a support and at least one phosphor layer provided thereon which comprises a binder and a stimulable phosphor dispersed therein, wherein the support is a resin film containing a white pigment.

Abstract: A instruction fetch look-aside buffer with a loop mode control provides for reduced storage contention by storing a program loop in a look-aside buffer during normal mode operations. When the loop is to be executed again loop mode is entered and the instructions are taken directly out of the look-aside buffer without any access of storage required. If the instructions in the look-aside buffer are invalidated during loop mode or if the program loop is exited normal mode operations are resumed.

Abstract: A method of assuring that each of a plurality of contemporaneously active database transactions comprising at least one read transaction and at most one update transaction has a consistent view of a database storing a plurality of versions of a relation. A transaction has a consistent view of a database if the data available to a transaction are not changed during its execution. An access dictionary is stored comprising an array of access blocks each defining the database location of one of the relation versions. At any given time, only one of the relation versions is defined as current. A relation dictionary comprising an array of relation blocks is stored such that as each database transaction is begun, a relation block associated with that database transaction is stored defining the access block defining the database location of the relation version then defined as current.

Abstract: UNLOAD and LOAD utility programs (24) in computer system memory (16) are used to transfer user and system data from one set of direct access storage devices (10, 12, 14) to the same or another set of direct access storage devices. The originating or sending system is off-loaded as a single complete entity by a system command to a sequential media (FIG. 3) following the Initial Program Loadable system load program. The system load program, when Initial Program Loaded on the receiving system, determines the new hardware configuration and alters the loaded system control information to reflect the new device types and device addresses and loads the system to the new DASD configuration and prepares it for normal processing on the new system.

Abstract: A process and apparatus for surface coating of workpieces in fluidized beds under atmospheric or slightly higher pressure is disclosed. The process comprises submerging the workpiece(s) in the fluidized bed, mixing a metal halide with an inert gas to form the fluidizing gas, feeding to the fluidized bed another gas which is capable of reacting with the metal halide in the fluidized bed and coating the workpiece(s). The workpiece(s) are maintained at a temperature in the range of from 1600.degree. F. to 2000.degree. F. until it is evenly coated. The apparatus comprises a saturator vessel for saturating the inert gas with the metal halide and a fluid bed reactor. There are several advantages that the present invention offers over the prior art, namely, the coating can be performed in a relatively short period of time, 4 to 5 hours and that atmospheric pressure can be used, eliminating the need for a costly vacuum system.

Abstract: A pyramidal data processing system comprising a plurality of levels of processor arrays, the number of processors in an array increases in number from a level of lowest resolution to a level of highest resolution. Each processor in an array is coupled for data transfer to a neighborhood of processors including laterally and diagnoally adjacent processors in the same level, a processor in the level of next lowest resolution, and processors in the level of next greatest resolution. A memory is associated with each processor to store value of data elements. A controller and control memory generate control signals to perform in synchrony data transformations on selected data elements associated with each neighborhood of processors.

Abstract: A radiation image storage panel comprising a support, a phosphor layer which comprises a binder and a stimulable phosphor dispersed therein, and a light-reflecting layer provided between the support and the phosphor layer which contains a white pigment, characterized in that said white pigment comprises alkaline earth metal fluorohalide represented by the formula M.sup.II FX, in which M.sup.II is at least one alkaline earth metal selected from the group consisting of Ba, Sr and Ca; and X is at least one halogen selected from the group consisting of Cl and Br.

Abstract: A microcomputer development system in which two jobs, such as a source program and an assembler program, can be run and monitored simultaneously. A CRT screen (10) is split so as to display information from both processor A (16) and processor B (18). A keyboard (12) is provided with a switch that toggles one of the processors so that the keyboard is assigned to that one processor to the exclusion of the other processor. In this case, the processor to which the keyboard is attached is designated the foreground processor, and its output is displayed highlighted on the CRT. The other processor is designated the background processor, and its information is displayed in reverse video to distinguish it from the foreground processor. At power-on reset time, processor A is designated the foreground processor and is assigned the keyboard. A printer (24) is always assigned to processor A. A disk controller (20) is shared by processor A and processor B, regardless of which processor is assigned to the keyboard.