Patents Examined by James Split
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Patent number: 8854034Abstract: A position detector having a plurality of sensor units is used. Each of the sensor units is configured to determine positions. The sensor units are selectively used for outputting positions of a moving object. Positional outputs are generated by combining outputs from a plurality of the sensor units in a segment where the plurality of sensor units output positions together, for allowing the positional outputs to change continuously from a start to an end of the segment.Type: GrantFiled: April 6, 2011Date of Patent: October 7, 2014Assignee: Murata Machinery, Ltd.Inventor: Tetsuya Shimizu
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Patent number: 8836360Abstract: A semiconductor device that can be manufactured with reduced costs and that includes a first connecting terminal, a second connecting terminal, a third connecting terminal, and a first circuit module configured to operate in response a first signal and a second signal. When a mode signal is in a first state, the first circuit module receives the first signal from the first connecting terminal and receives the second signal from the second connecting terminal. Otherwise, when the mode signal is in a second state, the first circuit module receives the first signal from the first connecting terminal and receives the second signal from the third connecting terminal. A memory module including at least one such memory device may also be provided.Type: GrantFiled: September 22, 2011Date of Patent: September 16, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Young-ju Oh
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Patent number: 8779783Abstract: Apparatuses and methods of mutual-capacitance sensing with a capacitance-sensing circuit, such as a self-capacitance sensing device (CSD). One apparatus includes an input node coupled to a capacitance sense pin to couple to a first electrode of a sense array, a transmit (TX) signal generation circuit to generate a TX signal to drive a second electrode of the sense array, logic circuitry coupled to the TX signal generation circuit and the input node. The logic circuitry is configured to selectively couple a first capacitor to the input node and a second capacitor to the input node timed with the TX signal. The apparatus further includes an analog-to-digital converter (ADC) coupled to receive a receive (RX) signal from the input node and to convert the RX signal into a digital value, the digital value representing a mutual capacitance between the first electrode and the second electrode.Type: GrantFiled: June 13, 2013Date of Patent: July 15, 2014Assignee: Cypress Semiconductor CorporationInventors: Carl F Liepold, Hans Van Antwerpen, John Kizziar, Hans Klein
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Patent number: 8773111Abstract: A current flowing through a switching element (5) of a power supply is detected by an AC current transformer (8), and a capacitor (201) is charged by a voltage corresponding to the current. A reduction factor of the terminal voltage of the capacitor in an off period of the switching element (5) is calculated based on an amplification factor of the terminal voltage of the capacitor, an absolute value of an instantaneous value of an input power supply voltage, and an instantaneous value of a direct current output voltage, and the capacitor is discharged so that the terminal voltage of the capacitor decreases by the reduction factor in an off period of the switching element (5). A current flowing through an inductor (4) is estimated from the terminal voltage of the capacitor.Type: GrantFiled: December 21, 2010Date of Patent: July 8, 2014Assignee: Fuji Electric Co., Ltd.Inventor: Yukihiro Nishikawa
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Patent number: 8766647Abstract: The transient load current of a circuit powered by a power distribution network is increased in a plurality of steps, with the step transition times being adjusted based on the transient noise of the power distribution network. This reduces the resonance noise that would otherwise occur in the supply current of the power distribution network.Type: GrantFiled: May 5, 2009Date of Patent: July 1, 2014Assignee: Rambus Inc.Inventors: Brian S. Leibowitz, Haechang Lee
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Patent number: 8760180Abstract: Methods and systems for compensating for temperature variation in the performance of electronic circuits and systems are disclosed. In some embodiments, the systems are configured to store compensation parameters determined in calibration, where the compensation parameters are used by the systems to modify performance. In some embodiments, the systems are part of an automatic test equipment (ATE) system.Type: GrantFiled: July 29, 2013Date of Patent: June 24, 2014Assignee: Analog Test EnginesInventor: Jeffrey Allen King
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Patent number: 8754634Abstract: Systems and methods for detecting the removal of a meter cover are provided. For example, a tamper-detect energy meter may include metering circuitry, a processor, a tamper detect switch, and a cover with a switch interface surface. The tamper detect switch may be triggered from an open circuit state to a closed circuit state as the switch interface surface of the cover contacts the tamper detect switch during removal.Type: GrantFiled: November 14, 2011Date of Patent: June 17, 2014Assignee: General Electric CompanyInventors: Subramanyam Satyasurya Chamarti, Bruce Joni Tomson, Michael George Glazebrook, Rathindra Nahar
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Patent number: 8749261Abstract: Embodiments of interfaces are disclosed. One such interface has a plurality of connector assemblies, each connector assembly in a single opening of a plurality of openings passing completely through the interface. Each connector assembly has first and second connectors that are electrically and physically coupled to each other.Type: GrantFiled: February 11, 2011Date of Patent: June 10, 2014Assignee: Micron Technology, Inc.Inventors: Scott Hoagland, Daniel Cram
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Patent number: 8742782Abstract: An on-chip technique for noncontact electrical testing of a test structure on a chip is provided. On-chip photodiodes receives pump light from a pump light source, where the on-chip photodiodes are electrically connected to the test structure and are configured to generate power for the test structure. An on-chip coupling unit receives probe light from a probe light source, where the on-chip coupling unit is optically connected to on-chip waveguides through which the probe light is transferred. On-chip switches open in response to receiving voltage output from the test structure, and the on-chip switches remain closed when the voltage output is not received from the test structure. The on-chip switches pass the probe light when opened by the voltage output from the test structure. The on-chip switches block the probe light by remaining closed, when the voltage output is not received from the test structure.Type: GrantFiled: July 27, 2011Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Xu Ouyang, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Patent number: 8710859Abstract: Disclosed is a method for testing multi-chip stacked packages. Initially, one or more substrate-less chip cubes are provided, each consisting of a plurality of chips such as chips stacked together having vertically connected with TSV's where there is a stacked gap between two adjacent chips. Next, the substrate-less chip cubes are adhered onto an adhesive tape where the adhesive tape is attached inside an opening of a tape carrier. Then, a filling encapsulant is formed on the adhesive tape to completely fill the chip stacked gaps. Next, the tape carrier is fixed on a wafer testing carrier in a manner to allow the substrate-less chip cubes to be loaded into a wafer tester without releasing from the adhesive tape. Accordingly, the probers of the wafer tester can be utilized to probe testing electrodes of the substrate-less chip cubes so that it is easy to integrate this testing method in TSV fabrication processes.Type: GrantFiled: September 23, 2011Date of Patent: April 29, 2014Assignee: Powertech Technology Inc.Inventor: Kai-Jun Chang
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Patent number: 8698504Abstract: A method is provided for detection of a ground fault in a high resistance network in a voltage source power conversion circuit comprising a power converter that converts incoming AC power to DC power applied to a DC bus and an inverter that converts DC power from the DC bus to output AC power. The method includes detecting a midpoint-to-ground voltage between a low side of the DC bus and a ground potential and detecting the presence of a ground fault in a high resistance network based upon the detected midpoint-to-ground voltage.Type: GrantFiled: October 9, 2010Date of Patent: April 15, 2014Assignee: Rockwell Automation Technologies, Inc.Inventors: Lixiang Wei, Zhijun Liu, Brian Patrick Brown, David W. Kirschnik, Russ J. Kerkman, Richard A. Lukaszewski, Gary Skibinski, Carlos Daniel Rodriguez-Valdez
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Patent number: 8659285Abstract: A current sensor, comprises an input conductor (IN) which is supplied with the current to be sensed and an output conductor (OUT) from which the current to be sensed is output. A conductor path is provided between the input conductor and the output conductor, wherein the path is provided on a first, movable element (1) and a second, fixed element (2). The path defines a pair of adjacent path portions (3,5; 3;4), one of the path portions (4;5) on the fixed element and the other (3) on one side of the movable element. An arrangement detects movement of the movable element to determine the current flowing. This arrangement uses a conductor path which can be part of the circuit being tested, and thereby does not require any additional components, other than the movement detector.Type: GrantFiled: October 9, 2009Date of Patent: February 25, 2014Assignee: NXP B.V.Inventor: Victor Zieren
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Patent number: 8633714Abstract: An impedance detection circuit includes a detection circuit, a correction circuit, a subtraction circuit, and an AC signal generator. The detection circuit has a first operational amplifier having an inverting input terminal coupled with one end of a signal line to whose other end a measured capacitor Cs is coupled, a non-inverting input terminal coupled with a shielding wire covering at least a part of the signal line and an output terminal of the AC signal generator, and an output terminal, and a second feedback resistor coupled between the output terminal and the inverting input terminal of the first operational amplifier. The correction circuit has a third resistor and a variable capacitor, and corrects a detection signal outputted from the first operational amplifier by adjusting a capacitance of the variable capacitor.Type: GrantFiled: May 6, 2011Date of Patent: January 21, 2014Assignee: Renesas Electronics CorporationInventor: Hiroaki Shirai
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Patent number: 8618827Abstract: Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.Type: GrantFiled: October 13, 2010Date of Patent: December 31, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Liang Shao, Shih-Wei Liang, Ying-Ju Chen, Ching-Jung Yang, Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu
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Patent number: 8618826Abstract: A short dummy test structure is disclosed, including a grounded shield layer above a substrate, at least two signal test pads, and a signal transmission line above the grounded shield layer and between the two signal test pads, wherein the signal transmission line is electrically coupled to the grounded shield layer. In one embodiment, the signal transmission line has a smaller total length than a total length of a corresponding signal transmission line and a device-under-test (DUT) of a test structure including the DUT. A de-embedding apparatus and method of de-embedding utilizing such a short dummy test structure are also disclosed.Type: GrantFiled: February 17, 2011Date of Patent: December 31, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Hsiu-Ying Cho
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Patent number: 8614581Abstract: A vacuum ionization gauge includes a cold cathode, a shield electrode, an anode ring, and a collector. The shield electrode includes a receiving space. The anode ring is located in the receiving space of the shield electrode. The cold cathode includes a field emission unit and a grid electrode corresponding to the field emission unit. The field emission unit includes at least one emitter. Each of the at least one emitter includes a carbon nanotube pipe. The carbon nanotube pipe has a first end, a second end, and a main body connecting to the first end and the second end. The second end has a plurality of carbon nanotube peaks.Type: GrantFiled: April 21, 2011Date of Patent: December 24, 2013Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Yang Wei, Shou-Shan Fan
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Patent number: 8610448Abstract: A one-sheet test device for testing panels on a one-sheet substrate and a test method thereof, wherein the test device and method are capable of performing a one-sheet test regardless of the number of panels formed on the one-sheet substrate. The one-sheet test device includes a signal supplier and a connection board. The signal supplier is for generating a plurality of signal groups and a plurality of dummy signals for testing the panels. The connection board is for transmitting a first signal group of the signal groups to a first panel of the panels corresponding to the first signal group, and for transmitting a signal of at least one signal group of the plurality of signal groups to at least two of the panels when the number of panels is larger than the number signal groups. The one-sheet test device may include a connection controller for controlling the connection board.Type: GrantFiled: October 7, 2010Date of Patent: December 17, 2013Assignee: Samsung Display Co., Ltd.Inventor: Sung-Woo Kim
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Patent number: 8593167Abstract: A method of testing a semiconductor device includes a conductive foreign matter test step of measuring the resistance value between the first and second conductive patterns to determine whether conductive foreign matter is present between the first and second conductive patterns, a first open circuit test step of measuring the resistance value between two points on the first conductive pattern to determine whether there is an open circuit in the first conductive pattern, and a second open circuit test step of measuring the resistance value between two points on the second conductive pattern to determine whether there is an open circuit in the second conductive pattern. The measurement of the resistance value in each of the test steps is accomplished by pressing probes vertically against the first conductive pattern or the second conductive pattern or both.Type: GrantFiled: March 8, 2011Date of Patent: November 26, 2013Assignee: Mitsubishi Electric CorporationInventor: Atsushi Narazaki
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Patent number: 8536875Abstract: A tester for a testing a Hard Disk Drive (HDD) flex circuit prior to electrical installation of a Head Gimbal Assembly (HGA) includes a shorting block that makes electrical contact to the bondpads on the sample. The shorting block includes one or more electrical contacts that are electrically grounded and have a size and/or configuration to contact the bondpads as well as the surface of the sample around the bondpads to accommodate positioning tolerances of the sample under test, without need for optics, precise probes, or precision stages. The electrical contacts of the shorting block may be, e.g., a matrix of pogopins or a flexible electrically-conductive material. During testing, the bondpads are shorted together and to ground with the shorting block while it is determined whether Short failures are properly detected. While the shorting block is not engaged with the bondpads, it is determined whether open failures are properly detected.Type: GrantFiled: October 12, 2010Date of Patent: September 17, 2013Assignee: Infinitum Solutions, Inc.Inventors: Wade A. Ogle, Henry Patland, Walter G. Bankshak, Jr.