Abstract: In accordance with one implementation the invention, a capacitor comprises two conductive capacitor electrodes separated by a capacitor dielectric layer, with at least one of the capacitor electrodes comprising at least one of Pt and Pd, and also comprising another metal which is capable of forming a conductive metal oxide when exposed to oxidizing conditions. In accordance with another. implementation, integrated circuitry includes a conductive silicon containing electrode projecting from a circuit node. A capacitor is received over the silicon containing electrode and comprises a first capacitor electrode having at least one of Pt and Pd, and also comprising another metal which is capable of forming a conductive metal oxide when exposed to oxidizing conditions. A high K capacitor dielectric layer received over the first capacitor electrode. A second capacitor electrode is received over the high K capacitor dielectric layer.

Abstract: A method for fabricating a flash memory is disclosed, in which a stacked gate structure comprising a floating gate and a control gate on the substrate is first formed. Ions are implanted into the substrate at one side of the stacked gate. A drain having a heavily doped region and a lightly doped region are subsequently formed. Spacers one each side of the stacked gate structure are formed. By using a photoresist layer covering the spacer at the drain end, the spacer at the source end can be reduced by an etching process. The source region of the flash memory is formed by implanting ions into the substrate using the reduced spacer as a mask.

Abstract: A packaged semiconductor device is provided which includes a semiconductor chip, a die pad for mounting the semiconductor chip, and at least one bondwire. The bondwire has a first end connected to the semiconductor chip, a second end opposite to the first end, and a transitional portion extending from the second end. The semiconductor device also includes at least one lead having an inner portion connected to the second end of the bondwire and an outer portion, and a resin package for enclosing the semiconductor chip, the die pad, the bondwire and the inner portion of the lead. An angle defined between the inner portion of the lead and the transitional portion of the bondwire is no greater than 15 degrees.

Abstract: This invention is directed to a method for reforming an undercoating surface prior to the formation of a film by the CVD technique using a reaction gas containing an ozone-containing gas having ozone contained in oxygen and TEOS. It effects the reform of the surface by forming an undercoating insulating film on a substrate prior to the formation of film and exposing the surface of the undercoating insulating film to plasma gas.

Abstract: A process for separating at least two elements of a structure. The two elements are in contact with one another along an interface and are fixed to one another by interatomic bonds at their interface. An ion implantation is performed in order to introduce ions into the structure with an adequate energy for them to reach the interface and with an adequate dose to break the interatomic bonds. This brings about at the interface, the formation of a gaseous phase having an adequate pressure to permit the separation of the two elements.

Abstract: Group III-V composites, which is used to manufacture Schottky contacts having the characteristics of higher energy gap, higher carriers mobility, etc., are applied for manufacturing high-speed devices. Therefore, in there years, Group III-V composite Schottky contacts are continuously being developed. In the invention, the surface treatment of composite semiconductor is used for reduce a surface state and oxidation, thereby increased the Schottky barriers of the Group III-V composite (such as, GaAs, fnP, InAs and InSb) Schottky contacts. During experiments. a phosphorus sulphide/ammonia sulphide solution and hydrogen fluoride solution are used for the surface treatment to increase the amount of sulphur contained on the surfaces of substrates, reduce the surface state and remove various oxides. Furthermore. ultra-thin and really stable sulphur fluoride/phosphorus fluoride layers having high energy gaps are formed on various substrates.

Abstract: A method of manufacturing an active panel results in a gate pad being formed so as to prevent being damaged by a probe pin during an auto probe testing process. An active panel made by the method includes a pad including a first conductive material an insulating layer on the pad, at least one contact hole exposing a portion of the pad, the insulating Layer covering a middle portion of the pad and a pad terminal connected to the pad through the at least one contact hole.

Abstract: A method is provided for forming an improved interconnect structure on a semiconductor body. A first metal layer is deposited on the semiconductor body. A sacrificial layer having a height is deposited on the first metal layer. The sacrificial layer and the metal layer are patterned to form separate metal lines with the sacrificial layer remaining on said metal lines. A low-k material is then deposited to fill the gaps between metal lines and to cover the sacrificial layer. The low-k material is then removed to a level within the height of the sacrificial layer. The sacrificial layer is then removed. A protective layer is deposited on top of the metal lines and the low-k material. A dielectric layer is deposited over the protective layer. The protective layer protects the low-k material from attack by chemicals utilized by subsequent process steps to etch vias in the dielectric layer, to strip photo-resist, and to clean the vias.

Abstract: The present invention provides a method of fabricating a field-effect transistor comprising the steps of forming a masking layer having an opening therein on laminated compound semiconductor layers, removing a portion of the laminated layers using an etching solution acting through the opening and creating a gate-forming recess having sidewalls tapering in a direction away from the masking layer, filling the gate-forming recess with gate metal and forming a gate electrode, and forming a recess around the gate electrode.

Abstract: A method for fabricating a bottom electrode is provided. In this method a dielectric layer is formed on a substrate having a source/drain region. A via hole is formed in the dielectric layer to expose the source/drain region. A patterned, doped polysilicon layer is formed on the dielectric layer and fills the via hole, wherein the cross-section of the patterned doped polysilicon layer is arced or polygonal. The surface of the patterned polysilicon layer is transformed into an amorphous silicon layer. A hemispherical-grain layer is formed on the amorphous silicon layer.

Abstract: A dual damascene manufacturing method includes utilizing a low dielectric constant material to form the dielectric layers and to prevent current due to the reduced line width. An implanting step is performed on the dielectric layers to reduce the incoherence and fragility of the dielectric layers, to densify the dielectric layers and to protect the dielectric layers from damage in the subsequent processes. The present invention utilizes the hard mask layer formed over the dielectric layer to reduce the difficulty of the depositing process of the barrier layer. The openings formed within the hard mask layer are broad at the top and narrow at the bottom. so that the barrier layer is more easily deposited into the opening and the subsequent deposition step of the conductive material layer is easily performed. Moreover, the hard mask layer can be utilized as the etching stop layer in the CMP process.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Abstract: A method of etching a platinum group metal film uses a gas mixture containing argon (Ar), oxygen (O2) and halogen gases and a method of forming a lower electrode of a capacitor uses the etching method. The gas mixture contains O2, Ar, and a third component, preferably a halogen, e.g., chlorine (Cl2) or hydrogen bromide (HBr). In the method of forming a lower electrode, a conductive film containing a metal belonging to a platinum (Pt) group is formed on a semiconductor substrate, a hard mask partially exposing the conductive film is then formed on the conductive film. Then, the exposed conductive film is dry-etched using the hard mask as an etching mask and a three-component gas mixture containing argon (Ar) and oxygen (O2), to form a conductive film pattern beneath the hard mask, and the hard mask is then removed.

Abstract: A high withstand voltage semiconductor device includes a semiconductor substrate of a first conductivity type, a metallic wiring formed on a surface of the semiconductor substrate and having a contact face with said semiconductor substrate, a highly doped impurity region formed within the semiconductor substrate below the contact face and of a second conductivity type, a lightly doped impurity region formed around the highly doped impurity region and of the second conductivity type, and a MOSFET with a second conductivity-type having a source or drain region formed on the surface of the semiconductor substrate and electrically connected to the metallic wiring through the impurity regions.

Abstract: A method of forming the gate structure of a MOS device forms a gate structure over a semiconductor substrate and then treats the sidewalls of the gate structure with nitrous oxide plasma so that the silicon and tungsten atoms within the gate structure can react with activated nitrogen in the plasma to form chemical bonds. Hence, a protective layer is formed on the gate sidewalls, thereby increasing thermal stability of the tungsten suicide layer and the polysilicon layer within the gate structure. Thereafter, an oxide material is formed over the protective layer using a rapid thermal oxidation. Next, spacers are formed over the sidewall oxide layer. Finally, subsequent operations necessary for forming a complete MOS device are performed.

Abstract: A method is provided for forming a stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling. This is accomplished by first depositing an unconventionally high or thick layer of nitride and then forming a shallow trench isolation (STI) through the nitride layer into the substrate, filling the STI with isolation oxide, removing the nitride thus leaving behind a deep opening about the filled STI, filling conformally the opening with a first polysilicon layer to form a floating gate, forming interpoly oxide layer over the floating gate, and then forming a second polysilicon layer to form the control gate and finally forming the self-aligned source of the stacked-gate flash memory cell of the invention. A stacked-gate flash memory cell is also provided having a shallow trench isolation with a high-step of oxide and high lateral coupling.

Abstract: An interlayer connection for electrically connecting first and second conductive elements and reducing interlayer registration requirements is disclosed. The interlayer connection includes a first layer including a first electrically conductive element, a second layer including a second electrically conductive element, and a third layer disposed between the first layer and the second layer. The third layer includes an electrically insulative portion having a matrix of immediately adjacent vias therethrough. A selected plurality of immediately adjacent vias within the matrix are disposed between the first and the second electrically conductive elements and contain electrically conductive material forming a conductive path between the first and the second electrically conductive elements.

Abstract: In a semiconductor device constituted using a borderless contact technique, for example, when a wiring layer with a damascene structure is connected to its underlying contact portion, a trench connect g with the contact portion is formed in the second interlayer insulation film. After that, the contact portion protruded from the bottom of the trench is selectively etched to flatten the bottom of the trench to remove a very small recess from that bottom of the trench which corresponds to a contact face between the contact portion and wiring layer. Thus, both a barrier metal layer and a metal layer for forming the wiring layer can be formed in the trench with higher reliability and accordingly the wiring layer and contact portion can be brought into reliable contact with each other. In a DRAM using a simple stacked capacitor, the storage electrode and plug portion can be put into reliable contact with each other.

Abstract: A method for forming a bottom storage node of a capacitor for a DRAM memory cell on a substrate is disclosed.

Abstract: A method of manufacturing a buried contact in an SRAM includes retaining a portion of the gate oxide layer adjacent to the source/drain region when a buried contact opening is formed. The retained gate oxide layer protects the substrate by acting as a buffer region, thus preventing the over-etching of substrate, which would form a deep trench. Consequently, contact resistance between the buried contact and the source/drain region is lowered, and leakage current at the junction is prevented.