Abstract: A method of fabricating a load resistor. The load resistor is often applied in a static random access memory. The interconnect between different conductive regions such as gate and source/drain region is formed by applying a hydrogen treatment to a refractory metal oxide layer, while the load resistors are formed by applying a hydrogen treatment with different parameters as the former one. The insulation is formed by the refractory metal oxide layer which is not to be covered.

Abstract: In a relative pressure sensor or miniaturized microphone as a micromechanical sensor component, a polysilicon membrane is arranged over a polysilicon membrane of an SOI substrate. A recess that is connected to the cavity between the membrane and the body silicon layer by openings in the body silicon layer is present in the substrate on the back side. Given an excursion of the membrane, a pressure equalization can therefore occur in the cavity as a result of these openings. The measurement occurs capacitatively by electrical connection of the electrically conductively doped membrane and a doped region formed in the body silicon layer.

Abstract: A semiconductor device having a controlled drive current strength is produced by varying dopant concentration to accommodate any variation in channel length, which is affected by variations in gate electrode dimension(s) from a desired value. After formation of the gate electrode on a substrate, its dimension(s) is measured and compared to a desired value. Based on any differences between the measured and desired values, the concentration of dopant implanted into the substrate is determined in order to counteract the variation in gate electrode dimension. This results in a change in dopant concentration that counteracts the effect of the variation in gate electrode dimension on the drive current strength. The present process provides enhanced control over the drive current strength of semiconductor devices and provides decreased variation within and between lots and corresponding increases in productivity.

Abstract: A method includes a self-aligned silicide (Salicide) technology in fabrication of an embedded dynamic random access memory (DRAM). On a silicon wafer, a first MOS transistor is formed in a logic device region, and second MOS transistor is formed in a memory device region. The improved method includes forming an insulating layer over the substrate at least covering the first (second) MOS transistor. A top portion of the insulating layer is removed to expose only a top portion of the first (second) gate structure. A portion of the insulating layer covering the first MOS transistor is removed to expose the first MOS transistor. Using the remaining insulating layer on the second MOS transistor as a mask, the Salicide fabrication process is performed to form a self-aligned silicide layer on the first interchangeable source/drain region, and the exposed top surface of the first (second) polysilicon gate structure.

Abstract: A pn junction is formed at a to-be-etched depth in an etching region of a semiconductor body and a reverse bias voltage is applied to the pn junction to form a depletion layer. Then, the semiconductor body is etched while monitoring the reverse bias current flowing via the pn junction and a point at which the bias current has abruptly increased is determined as the etching end point.

Abstract: A method of forming a bottom storage node of a capacitor on a substrate is disclosed.

Abstract: A method of forming a layer of hemispherical grain polysilicon over the lower electrode of a capacitor. The method comprises the steps of providing a substrate that has a field effect transistor already formed thereon, and then forming an insulating layer with a contact opening over the substrate. Subsequently, a polysilicon layer is formed over the insulating layer that completely fills the contact opening. This polysilicon layer is electrically coupled to one of the source/drain regions of the field effect transistor. Thereafter, a thin buffer layer is formed over the polysilicon layer, and then the thin buffer layer is patterned. The thin buffer layer is used as a mask for covering the polysilicon layer that is to be part of the lower electrode of a capacitor. Next, a plasma etching operation is carried out to remove the thin buffer layer and a portion of the polysilicon layer at the same time.

Abstract: A method of forming a silicon layer includes the step of calibrating the heater temperature so that a predetermined temperature is maintained when a microelectronic substrate is subsequently heated despite a number of processing runs previously performed. This calibrating step includes loading a test substrate into the reaction chamber, subjecting the test substrate to the predetermined reaction recipe wherein the test substrate is heated according to the predetermined recipe, measuring the temperature of the substrate, and removing the test substrate from the reaction chamber. The heater temperature is then adjusted according to the measured temperature of the test substrate. A microelectronic substrate is then loaded into the reaction chamber, and a hemispherical grained silicon seed layer is formed on the microelectronic substrate according to the predetermined recipe.

Abstract: A method of manufacturing semiconductor devices wherein a partially completed semiconductor device having a first and second layer of interlayer dielectric and a first and second etch stop layer has the second etch stop layer masked and etched with an etch pattern having dimensions of the trench structure to be formed in the second interlayer dielectric. The second layer dielectric and first etch stop layer are then masked and etched with an etch pattern having dimensions of the via structure to be formed in the first interlayer dielectric. The remaining portions of the photoresist is removed and exposed portions of the second layer of interlayer dielectric and the first layer of interlayer dielectric are then etched simultaneously. The via structure and trench structure are then simultaneously filled with a conductive material.

Abstract: A method of fabricating a capacitor. Isolation layers and conductive layers are formed alternately on a dielectric layer on a substrate. The conductive layers and the isolation layers are patterned to form an opening to expose a conductive region of the substrate. A spacer is formed on the sidewall of the conductive layers and the isolation layers exposed by the opening. The spacer is used as a mask to form a contact hole. The conductive layer on the dielectric layer is used as an etching stop layer. The isolation layers and the conductive layers are patterned. A conductive layer is formed to cover the substrate to cover the isolation layers and the conductive layers and to fill the contact hole. A portion of the conductive layers is removed to expose the spacer. The spacer and isolation layers are removed to expose the storage electrode formed by the conductive layers. A dielectric film layer and a cell electrode are formed in sequence over the substrate.

Abstract: A method of manufacturing a crystalline silicon film excellent in crystallinity. When using elements such as nickel as metal elements that promotes the crystallization of the amorphous silicon film, nickel is allowed to be contained in a solution repelled by the surface of the amorphous silicon film. Then, a part of the amorphous silicon film is removed, and the solution is held in only that part. In this way, the nickel elements are selectively introduced into a part of the amorphous silicon film, and a heat treatment is also conducted to allow crystal growth to proceed from that portion toward a direction parallel to a substrate.

Abstract: Methods for manufacturing microelectronic using chemical mechanical polishing (CMP) comprises providing wafers wetted with deionized water mixtures having first pHs, and performing CMP on the wetted wafers while applying polishing slurries having second pHs thereto. In accordance with the invention, the first pHs are substantially equal to the second pHs.

Abstract: A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact.

Abstract: A method for manufacturing an inductor with resonant frequency and Q value increased in semiconductor process can reduce substrate coupling effect, because (an) air layer(s) is/are formed just under a spiral metal layer which functions as an inductor. In addition, part of the substrate material still remains around the air layer(s), which can be used as a support for the spiral metal layer. Therefore, a problem causing the above-mentioned spiral metal layer to collapse will never occur.

Abstract: A self-aligned protection diode is formed at the first polycrystalline silicon level, thereby enabling in-process charging damage protection while reducing the layout area. The self-aligned protection diode is formed by providing an etch stop layer having an arcuate portion with different etching characteristics than horizontal portions, isotropically etching the arcuate portion to form a through hole exposing a side surface of a polycrystalline silicon layer and the underlying semiconductor substrate, ion implanting impurities to form the protection diode, and filling the through hole with a metal interconnecting the side surface of the polycrystalline silicon layer with the vertically self-aligned protection diode.

Abstract: A top surface of a wafer, at which semiconductor devices are formed, is bonded to an auxiliary plate by means of a first wax. In a state where the auxiliary plate is bonded to a polishing jig by means of a second wax, a bottom surface of the wafer, at which a sapphire substrate is provided, is polished. The second wax is melted and the auxiliary plate is removed from the polishing jig. In this state, scribe lines are formed in the bottom surface of the wafer according to a device separation pattern. Then, the bottom surface of the wafer is attached to an adhesive sheet, following which the first wax is melted and the wafer is removed from the auxiliary plate 105. Subsequently, the adhesive sheet is extended and the wafer is divided into the devices along the scribe lines.