Patents Examined by Jane Wei
  • Patent number: 11079955
    Abstract: Examples relate to an approximative memory deduplication method, a controller apparatus or controller device for a memory or storage controller, a memory or storage controller, a computer system and to a computer program. The approximative memory deduplication method comprises determining a hash value of a data block. The hash value is based on a user-defined approximative hashing function. The approximative memory deduplication method comprises storing a quantized version of the data block based on the hash value using a memory or storage device of the computer system.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Mustafa Hajeer, Thomas Willhalm, Amin Firoozshahian, Chandan Egbert
  • Patent number: 11074171
    Abstract: A data storage device is provided. The data storage device a buffer configured to store a mapping table comprising physical block addresses (PBAs) corresponding to logical block addresses (LBAs), a non-volatile memory configured to store data; and a controller configured to control the buffer and the non-volatile. The controller is configured to read data stored at a first PBA of the non-volatile memory corresponding to a first LBA by referring to the mapping table when receiving a command to read data corresponding to the first LBA from outside of the data storage device, and, when a second LBA included in the data read from the non-volatile memory is different from the first LBA, retry reading, from the non-volatile memory, the data corresponding to the first LBA.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: July 27, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo Hyun Kim, Dong-Young Seo, Sang Kwon Moon
  • Patent number: 11068393
    Abstract: Garbage collection (GC) to reclaim memory in computing systems sometimes suspends applications, web services, and other mutator programs in order to scan their execution stacks, which reduces their responsiveness. But suspension times are decreased by behavior-driven stack scan optimization (BDSSO) functionality that increases the concurrency of mutator execution with GC stack scanning. BDSSO obtains execution stack frame occurrence data, determines frame execution likelihoods, selects a stack scan depth based on the likelihoods, and installs a scan return barrier at the selected depth. Then the GC scans the execution stack below the barrier while the mutator runs, thus increasing concurrency and improving mutator responsiveness. Selected barrier locations vary according to actual stack activity to provide optimized concurrency instead of using an inflexible approach to barrier placement. Existing profiler samples or virtual machine interfaces can be reused by BDSSO.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: July 20, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Aditya Mandaleeka
  • Patent number: 11068175
    Abstract: A system including a storage drive and a semiconductor apparatus coupled to the storage drive, is provided. The semiconductor apparatus may include one or more substrates and logic coupled to the one or more substrates, the logic coupled to the one or more substrates to: initiate managing resources of the storage drive and, if the storage drive loses capacity, determine an amount of capacity loss, create a reserved file that is associated with logical memory space in a file system, based on the amount of the capacity loss, and erase at least a portion of the reserved file so that logical memory space associated with an un-erased portion of the reserved file is usable by the storage drive.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: Marcin Pioch, Michael Mesnier, Anand Ramalingam, Benjamin Boyer, Kapil Karkra, Piotr Wysocki
  • Patent number: 11061728
    Abstract: A system and method for allocating memory to a heterogeneous address space includes identifying, by an operating system, at least one superset feature from an application configured to be executed on a host device. The address space associated with the application includes a plurality of supersets, and wherein the operating system allocates the memory to each of the plurality of supersets from a non-volatile memory or a volatile memory based upon the at least one superset feature.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: July 13, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
  • Patent number: 11061584
    Abstract: Methods and apparatus for profile-guided preloading for virtualized resources are described. A block-level storage volume whose contents are to be populated via data transfers from a repository service is programmatically attached to a compute instance. An indication of data transfers from the repository to a block storage service implementing the volume is obtained, corresponding to a particular phase of program execution at the compute instance. A storage profile is generated, based at least in part on the indication of data transfers. The storage profile is subsequently used to pre-load data from the repository service on behalf of other compute instances.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: July 13, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Marcin Piotr Kowalski, David R. Richardson, James Alfred Gordon Greenfield, Jacobus Johannes Nicolaas Van Der Merwe, Matthew James Eddey, Christopher Richard Jacques De Kadt, Peter Nicholas Desantis
  • Patent number: 11061599
    Abstract: An aspect of volume migration includes establishing a connection between hosts and a non-volatile memory over fabric (NVMeoF) controller for appliances, and creating and exposing a volume as a namespace to hosts. The namespace forms part of an asymmetric namespace access (ANA) group in which optimized paths are exposed to the hosts. Upon receiving a request to migrate the volume from a source appliance to a destination appliance, an aspect further includes creating a namespace on the destination, and configuring the ANA group of the namespace as inaccessible. Through the connection, an aspect includes initiating an asynchronous event notification (AEN) to the host to connect ports on the destination and, upon connecting to the ports, discovering by the hosts on the destination, the namespace created, verifying the hosts have connected to the ports and have discovered the namespace, and migrating data to the destination and performing input/output cutover.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: July 13, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Mukesh Gupta, Dmitry Tylik
  • Patent number: 11048646
    Abstract: A method for limiting I/O access in shared storage systems is disclosed. In one embodiment, such a method includes establishing, for a volume, a list of address spaces that are authorized to access the volume. The method further receives an I/O request to access the volume and determines whether the I/O request originates from one of the address spaces identified in the list. If the I/O request originates from one of the address spaces in the list, the method passes the I/O request to the volume. If, on the other hand, the I/O request does not originate from one of the address spaces in the list, the method blocks the I/O request. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: April 21, 2018
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dash D. Miller, Tabor R. Powelson, David C. Reed, Jamie Storey
  • Patent number: 11048654
    Abstract: Systems, apparatus and methods are provided to combine multiple channels in a multi-channel memory controller to save area and reduce power and cost. An apparatus may comprise a first memory controller configured to access a first channel using a first protocol, a second memory controller configured to access a second channel using a second protocol that is different from the first protocol and a physical interface coupled to the first memory controller and a second memory controller. The physical interface may comprise a set of pins for an address and command bus shared by the first memory controller and the second memory controller for the first memory controller and the second memory controller to send address or command to respective channels by time division multiplexing.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: June 29, 2021
    Assignee: INNOGRIT TECHNOLOGIES CO., LTD.
    Inventors: Shawn Chen, Wei Jiang, Lin Chen
  • Patent number: 11042479
    Abstract: Techniques are provided for providing a fully active and non-replicated block storage solution in a clustered filesystem that implements cache coherency. In a clustered filesystem where one or more data blocks are stored in a respective cache of each host node of a plurality of host nodes, a request is received at a host node of the plurality of host nodes from a client device to write the one or more data blocks to a shared storage device. In response to the request, the one or more data blocks are stored in the cache of the host node and a particular notification is sent to another host node of the plurality of host nodes that the one or more data blocks have been written to the shared storage device. In response to receiving the notification, the other host node invalidates a cached copy of the one or more data blocks in the respective cache of the other host node.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: June 22, 2021
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Donald Allan Graves, Jr., Frederick S. Glover, Alan David Brunelle, Pranav Dayananda Bagur, James Bensson
  • Patent number: 11030096
    Abstract: Preparing a key block in a memory system. Various methods include: selecting a candidate key block of memory; checking a quality of the candidate key block using a word line of the candidate key block; altering operating parameters of the candidate key memory block; and registering the candidate key memory block as the key block. Where altering the operating parameters includes replacing a first set of parameters associated with the first memory block with a second set of parameters, where the first set of parameters includes a first erase parameter, a first program parameter, and a first read parameter, where the memory block operating in a normal block mode is accessed using the first set of parameters, and the second set of parameters includes a second erase parameter, a second program parameter, and a second read parameter, where the first memory block is accessed using the second set of parameters.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: June 8, 2021
    Inventors: Niles Yang, Sahil Sharma, Rohit Sehgal, Phil Reusswig
  • Patent number: 11024352
    Abstract: A spatial disturbance that occurs when an access is concentrated in a specific memory area in a volatile semiconductor memory like DRAM is properly solved by a memory controller. The memory controller includes a concentration access detection part generating a concentration access detection signal when an address for accessing a specific memory area among memory areas of volatile semiconductor memory is concentratedly received. In the case that the concentration access detection signal is generated, the memory controller includes a controller for easing or preventing corruption of data which memory cells of the specific memory area and/or memory cells of memory areas adjacent to the specific memory area hold.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 1, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyo Min Sohn, Dong Su Lee, Young Jin Cho, Hyung Woo Choi
  • Patent number: 11023138
    Abstract: A non-volatile storage system, configured to use a protocol that supports predictable latency, including: a memory array storing a data in a block of memory; a controller coupled to the memory array, where the controller is configured to: in response to determining that predictable latency is enabled, operate the storage system using a first mode for a duration of time, where during the first mode, the storage system operates such that a read latency is below a read latency threshold; and after the duration of time, operate, the storage system using a second mode for a second duration of time, where during the second mode: the storage system performs a management operation based on a second set of thresholds that are different from a first set of threshold used during the first mode.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 1, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ariel Navon, Shay Benisty, Alexander Bazarsky
  • Patent number: 11016667
    Abstract: A method for mapping LUNs (logical unit numbers) in storage memory, performed by a storage system, is provided. The method includes determining a set of LUNs in the storage memory and generating a mapping from a logical address space to all of the LUNs in the set, based on the determining, so that each logical address in the logical address space maps to one LUN in the set. The method includes accessing one or more of the LUNs in accordance with the mapping.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: May 25, 2021
    Assignee: Pure Storage, Inc.
    Inventor: Russell Sears
  • Patent number: 11016848
    Abstract: In a data storage system with distributed data storage units, initialization-less parity can be practiced with a storage controller connected to a storage memory and multiple data storage units. Data locations of data storage devices of the respective data storage units can be arranged as distributed data storage groups as directed by the storage controller prior to receiving a write request to a distributed data storage group. Unwritten data locations of the distributed data storage group are identified by consulting the storage memory and each unwritten data storage location may be assumed to have a zero value when computing parity data for the distributed data storage group.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: May 25, 2021
    Assignee: Seagate Technology LLC
    Inventor: Chetan Bendakaluru Lingarajappa
  • Patent number: 11010290
    Abstract: Exemplary embodiments of the disclosure provide a memory management method for a rewritable non-volatile memory module including the following steps. A host write operation is performed to receive a write command from a host system and store a first data corresponding to the write command to a first physical unit. A first updating data corresponding to the host write operation is recorded. A data merge operation is performed to read a second data from a second physical unit and store the second data to a third physical unit. A second updating data corresponding to the data merge operation is recorded. A management information is read from the rewritable non-volatile memory module to a buffer memory and updated in the buffer memory according to the first updating data and the second updating data.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: May 18, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 11010299
    Abstract: Systems and methods for pre-fetching data in a memory device are disclosed. The method may include receiving a current read command and determining whether the current read command is a random read command, for example based on a data chunk length identified by the current read command. The method may further include updating a prior read command data structure with the current read command, for random read commands; determining a predicted next read command from the prior read command data structure based on the current read command; and pre-fetching data associated with the predicted next read command. Functionality for prediction of next read commands, or pre-fetch of predicted next read commands, may be turned on or off based on resource availability or prediction success rate measurements.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: May 18, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ariel Navon, Eran Sharon, Idan Alrod
  • Patent number: 10997066
    Abstract: A storage device includes a descramble module configured to descramble at least a portion of a read command, which includes logical block address (LBA) information and first meta information, into first signature information and first physical address (PA) information, for accessing a flash memory. A compare module is provided, which is configured to compare the first signature information against stored signature information to thereby determine an equivalency or discrepancy therebetween. An access module is provided, which is configured to use the first PA information to access a data region of the flash memory, upon determination of the equivalency by said compare module.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: May 4, 2021
    Inventors: Dong-Woo Kim, Jae Sun No, Song Ho Yoon, Kyoung Back Lee, Wook Han Jeong
  • Patent number: 10996883
    Abstract: A storage system includes a host device and a storage device. The host device generates a write command, a logical address of write data corresponding to the write command, and a selective purge tag indicating that the write data are targeted for selective purge. The storage device receives the write command, the logical address, and the selective purge tag, stores write data, and logically erases the stored write data upon receiving an erase command from the host device. In addition, the storage device physically erases the stored write data upon receiving a selective purge request from the host device.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: May 4, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Min Kim, Songho Yoon
  • Patent number: 10983709
    Abstract: Methods, non-transitory computer readable media, and computing devices that execute a storage operation, without journaling the storage operation in a log, and withhold from a file system a list of freed inodes including an indication of an inode freed as a result of the execution of the storage operation. A consistency point operation is then initiated that retrieves storage operations logged as journal entries in the log and commits a result of each of the storage operations to data storage devices. A list of available inodes is updated based on the list of freed inodes, when the consistency point operation is determined to be complete. This technology reduces the number of storage operations that are required to be journaled to maintain consistency of a file system, thereby reducing the runtime resources required to facilitate the journaling and replay resource required to replay the storage operations following a recovery.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: April 20, 2021
    Assignee: NETAPP, INC.
    Inventors: Ram Kesavan, Ananthan Subramanian, Hiroshi Ishii, Abdul Basit, Joseph Brown, Rohit Singh