Abstract: The invention introduces a non-transitory computer program product for scheduling execution of host commands when executed by a processing unit of a flash controller. Space of a random access memory of the flash controller is allocated for a first queue and a second queue, and the first queue stores the host commands issued by a host side in an order of time when the host commands arrive to the flash controller. The non-transitory computer program product includes program code to: migrate one or more host write commands from the top of the first queue to the second queue in an order of time when the host write commands arrive to the flash controller until the top of the first queue stores a host read command; fetch the host read command from the top of the first queue; execute the host read command to read user data from a flash module; and reply to the host side with the user data.

Abstract: Various embodiments of the present application set forth a computer-implemented method for accessing data comprising identifying a first set of read operations occurring during a first time period, where each read operation included in the set of read operations is associated with retrieving a different portion of at least one object from a storage system, determining a byte density associated with the set of read operations, where the byte density indicates a size of contiguous portions of the at least one object that were retrieved during the first time period, and determining, based on the byte density, a pre-buffering block size for a read operation during a second period, where the pre-buffering block size specifies a size of a portion of at least one object that is to be retrieved from the storage system.

Abstract: Discovery service contact information is provided from a data storage system to administration logic of a virtualization environment, and distributed within the virtualization environment to hypervisor hosts, enabling the hypervisor hosts to discover logical ports within the data storage system, and then establish logical communication paths between the hypervisor hosts and the ports. In response to determining that the data storage system supports virtual volumes, the hypervisor hosts indicate hypervisor capability of using virtual volumes to the data storage system, and the data storage system exposes virtual volumes to hypervisors in response to indications of the ability of those hypervisors to use virtual volumes.

Abstract: An apparatus is described. The apparatus includes an accelerator to be coupled to a memory region that the accelerator shares with a virtualization environment comprising a guest OS, a guest VM and an SSD device driver. The accelerator is to forward a submission queue doorbell setting made by the SSD device driver in the shared memory to a corresponding submission queue doorbell in an SSD controller.

Abstract: A computer program product, system, and method to manage access to storage resources from multiple applications. A plurality of virtual controllers is generated in a host memory space. Each virtual controller includes at least one virtual namespace that maps to a physical namespace in a physical controller. Applications are assigned to the virtual controllers. For each application of the applications assigned one of the virtual controllers, a virtual submission queue is generated to communicate with the virtual controller assigned to the application. An Input/Output (I/O) request to a target virtual namespace in one of the virtual submission queues is added to a physical submission queue for the physical controller having the physical namespace for which the target virtual namespace was generated.

Abstract: The present invention provides a method performed by a secure digital (SD) card supporting both an SD mode and a peripheral component interconnect express (PCIe) mode for initializing the SD card. The method includes: (a) after receiving a first supply voltage through a first voltage supply pin from a host coupled to the SD card, entering the SD mode if the SD card is not in the PCIe mode and a CMD0 command for entering the SD mode is received through a command pin from the host coupled to the SD card; and (b) after receiving the first supply voltage through the first voltage supply pin from the host coupled to the SD card, performing a PCIe linkup process if the SD card is not in the SD mode and a second supply voltage is received through a second voltage supply pin from the host coupled to the SD card. The SD card enters the PCIe mode if the PCIe linkup process succeeds.

Abstract: A disclosed example to use an erase-suspend feature on a memory device includes a host interface to receive a first erase command to perform an erase operation; and a control circuit to: based on the erase-suspend feature being enabled at the memory device, suspend the erase operation based on determining that a length of time equal to an erase segment duration value has elapsed, the length of time elapsed being relative to a start of an erase segment, and the erase segment duration value specified in a configuration parameter for the erase-suspend feature; perform a second memory operation when the erase operation is suspended; and after the second memory operation is complete, resume the erase operation based on receiving a second erase command from the memory host controller.

Abstract: An information processing apparatus includes an adjustment unit configured to adjust a write condition to reduce a capacity of data to be written to a first storage unit before starting predetermined processing including processing for writing data to the first storage, the write condition being a condition for writing data to the first storage unit, and a restoration unit configured to restore the write condition to an original condition set before the write condition is adjusted by the adjustment unit, after completion of the predetermined processing.

Abstract: Techniques involve receiving a write request for writing metadata of a file system into a solid state disk having a multi-level cell, and then caching the to-be-written metadata into a memory. The techniques further involve sequentially writing the cached metadata into the solid state disk by redirect-on-write. Accordingly, there is a file system implemented for properties of a solid state disk having a multi-level cell. Such techniques are able to provide completely sequential write of metadata of the file system by supporting redirect-on-write, thereby reducing the write amplification of the solid state disk and improving the performance of the file system.

Abstract: A device can include a plurality of processing sources; a multiplexer (MUX) configured to assign read requests from the processing sources to predetermined time division multiplexer (TDM) command slots. A memory controller can generate nonvolatile memory (NVM) command and address data from read requests received from the MUX during the TDM command slots assigned to the read requests on a unidirectional command-address bus. The address data can include at least a bank address. The device can also receive read data on a unidirectional parallel data bus in synchronism with rising and falling edges of a received data clock. The read data can be received in TDM read slots having a predetermined order. A demultiplexer can provide the read data of each TDM read slot to one of the processing sources based on the TDM read slot position in the predetermined order. Related methods and systems are also disclosed.

Abstract: A memory management system, such as a virtual memory manager that manages a virtual memory space that includes volatile memory (e.g. DRAM) and non-volatile memory (e.g., flash memory) creates a reserved portion of memory in the volatile memory for at least one user application in one embodiment, and that reserved portion can also store content that it restricted to read only permission within the non-volatile memory.

Abstract: A virtual non-volatile memory system includes a BIOS coupled to a non-volatile storage system and a volatile memory system. The BIOS designates a portion of the volatile memory system as a virtual NVDIMM, reserves a portion of the non-volatile storage system for storing virtual NVDIMM data, reports the virtual NVDIMM to an operating system using an ACPI NFIT, and emulates an NVDIMM controller. When a virtual NVDIMM storage event occurs, the BIOS copies data from the portion of the volatile memory system designated as the virtual NVDIMM to the portion of the non-volatile storage system reserved for storing virtual NVDIMM data. When the BIOS subsequently determines that a virtual NVDIMM recovery event has occurred, it copies the data stored in the portion of the non-volatile storage system reserved for storing virtual NVDIMM data to the portion of the volatile memory system designated as the virtual NVDIMM.

Abstract: Apparatuses and methods for managing a coherent memory are described. These may include one or more algorithmic logic units (ALUs) and an input/output (I/O) interface. The I/O interface may receive one or more commands and retrieve data from or write data to a memory device. Each command may contain a memory address portion associated with a memory device. The apparatus may also include a memory mapping unit and a device controller. The memory mapping unit may map the memory address to a memory portion of the memory device, and the device controller may communicate with the memory device to retrieve data from or write data to the memory device. The apparatus may be implemented as a processing element in a configurable logic block network, which may additionally include a control logic unit that receives programming instructions from an application and generate the one or more commands based on the instructions.

Abstract: A clustered memory system includes a first computing system coupled to a second computing system via a network, and including a clustered memory management subsystem coupled to a central processing subsystem and a networking device. The clustered memory management subsystem receives a processor memory-centric access request associated with a memory access operation from the central processing subsystem, and uses memory management hardware to determine that the processor memory-centric access request is directed to a second memory subsystem in the second computing system. The clustered memory management subsystem then uses remote memory access hardware to generate memory access information for performing the memory access operation at the second memory subsystem, and instructs the networking device to utilize the memory access information to transmit at least one memory access communication that provides for the performance of the memory access operation at the second memory subsystem.

Abstract: A processing device of a memory sub-system can monitor a plurality of received commands to identify a forced unit access command. The processing device can identify a metadata area of the memory device based on the forced unit access command. The processing device can also perform an action responsive to identifying a subsequent forced unit access command to the metadata area.

Abstract: According to one embodiment, a memory system includes a memory system includes a first nonvolatile memory and a controller. The controller controls the first nonvolatile memory. The second memory system includes a second nonvolatile memory. The controller manages information indicative of correspondences between private logical addresses and public logical addresses. The private logical addresses include first private logical addresses and second private logical addresses. Each of the first private logical addresses specifies a location in a first logical address space corresponding to the first nonvolatile memory. Each of the second private logical addresses specifies a location in a second logical address space corresponding to the second nonvolatile memory.

Abstract: A method, computer program product, and computer system for maintaining a federation of a plurality of appliances as a single subsystem, wherein maintaining the federation as the single subsystem may include maintaining a centralized discovery mechanism across the plurality of appliances, wherein a discovery service of the centralized discovery mechanism may return a list of all ports in the federation. Controller IDs for a predefined range of controller IDs may be allocated for a plurality of dynamic controllers per appliance of the plurality of appliances, wherein the controller IDs may be allocated as a response to a connect command from a host. An empty namespace list for the plurality of dynamic controllers on the plurality of appliances in the federation may be exposed. The host may receive a notification from at least one dynamic controller of the plurality of dynamic controllers on at least one appliance of the plurality of appliances in the federation.

Abstract: Methods, systems, and devices related to host identification for a memory system are described. A memory system may receive an index value from a host system that is associated with an identification of the host system. The memory system may identify one or more operating parameter associated with the index value based on receiving the index value. The memory system controller may configure the memory system to utilize one or more operating parameters associated with the index value based on identifying the operating parameters. The memory system may output an indication to the host system that the operating parameters associated with the index value are configured to be utilized by the memory system.

Abstract: A data storage device includes a memory device and a controller. The memory device includes a rare open block that stores data corresponding to a re-allocated invalid logical address and a normal open block that stores data corresponding to a newly allocated free logical address. The controller determines whether to store write data in the rare open block or the normal open block based on information included in a write command received from a host, and controls the memory device to store the write data in the rare open block or the normal open block according to a result of the determination.

Abstract: In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the fir