Patents Examined by Jane Wei
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Patent number: 11294812Abstract: Provided are a computer program product, system, and method for prefetching cache resources for a write request from a host to tracks in storage cached in a cache. Cache resources held for a plurality of tracks in a write set are released before expected writes are received for the tracks in the write set. Cache resources for tracks in the write set are obtained, following the release of the cache resources, to use for expected write requests to the tracks in the write set.Type: GrantFiled: August 4, 2020Date of Patent: April 5, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Beth Ann Peterson, Chung Man Fung, Matthew J. Kalos, Matthew Richard Craig
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Stacked memory device performing function-in-memory (FIM) operation and method of operating the same
Patent number: 11281397Abstract: A stacked memory device includes a plurality memory semiconductor dies, a plurality of through silicon vias, a function-in-memory (FIM) front-end circuit and a plurality of FIM back-end circuits. The buffer semiconductor die is configured to communicate with a host device. The memory semiconductor dies are stacked on the buffer semiconductor die, and include a plurality of memory banks. The through-silicon vias electrically connect the buffer semiconductor die and the memory semiconductor dies. The FIM front-end circuit receives a plurality of FIM instructions for a FIM operation from the host device, and stores the FIM instructions. The FIM operation includes data processing based on internal data read from the memory banks. The FIM back-end circuits are respectively included in the memory semiconductor dies. The FIM back-end circuits perform the FIM operation corresponding to the plurality of FIM instructions stored in the FIM front-end circuit under control of the FIM front-end circuit.Type: GrantFiled: September 2, 2020Date of Patent: March 22, 2022Inventors: Seongil O, Kyomin Sohn -
Patent number: 11262938Abstract: A method and associated apparatus for performing access management of a memory device with aid of dedicated bit information are provided. The method includes: transmitting a compact hybrid table comprising multiple compressed tables to a host device, for being stored in the host device, to allow the host device to send one of multiple compact hybrid table entries of the compact hybrid table to the memory device as reading reference; determining a starting logical address and a data length according to a read command packet from the host device, and determining a first mapping relationship and the dedicated bit information according to the read command packet; determining second mapping relationship(s) according to the first mapping relationship and the dedicated bit information; and reading the data from the NV memory for the host device at least according to the first mapping relationship and the second mapping relationship(s).Type: GrantFiled: October 28, 2020Date of Patent: March 1, 2022Assignee: Silicon Motion, Inc.Inventor: Yu-Chih Lin
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Patent number: 11256441Abstract: Provided is a semiconductor system. The semiconductor system includes a universal flash storage (UFS) host, including a host controller interface, a UniPro and a M-PHY; a UFS device configured to exchange data with the UFS host through a UFS interface; and an application processor configured to control the UFS host. The UFS device is configured to maintain a power-on status when the application processor operates in a suspend mode.Type: GrantFiled: February 19, 2020Date of Patent: February 22, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Hyun-Seung Seo
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Patent number: 11249676Abstract: A flash memory controller includes a read-only memory, a microprocessor and a buffer memory, wherein the buffer memory includes a data temporary storage area having continuous addresses. When the flash memory controller receives data from a host device, the microprocessor determines whether there is enough space between the last stored data in the data temporary storage area and an end address of the data temporary storage area to store the entire content of the data. If there is not enough space between the last stored data in the data temporary storage area and the end address to store the entire content of the data, the microprocessor directly stores the data from a starting address in the data temporary storage area, without writing any part of the data to the area before the end address of the data temporary storage area.Type: GrantFiled: November 1, 2020Date of Patent: February 15, 2022Assignee: Silicon Motion, Inc.Inventor: Wen-Sheng Lin
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Patent number: 11231871Abstract: The present invention detects a battery abnormality during a driving cycle or self-shutdown even when a battery voltage sensor is not mounted. In the present invention, a first storage region is provided with a failure information storage region and a second storage region management information storage region, a second storage region is provided with a failure information storage region and a first storage region management information storage region, and a management information access flag storage region for storing access information indicating a presence or absence of an access to management information of the first storage region and management information of the second storage region is provided separately from the first storage region and the second storage region.Type: GrantFiled: February 1, 2019Date of Patent: January 25, 2022Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.Inventor: Kenji Masuda
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Patent number: 11204706Abstract: A method for generating one or more hashes for one or more data blocks is provided. The method receives a data block to write on at least one physical disk of a set of physical disks associated with a set of host machines. The method then calculates a hash for the received data block and writes a first entry to a data log in a cache disk, the first entry comprising a first header and data indicative of the received block, the first header comprising the hash. The method further writes the data to the at least one physical disk as part of data blocks of a stripe, and stores the hash in a summary block on the at least one physical disk. The summary block is associated with the data blocks of the stripe stored on the at least one physical disk.Type: GrantFiled: March 23, 2020Date of Patent: December 21, 2021Assignee: VMware, Inc.Inventors: Wenguang Wang, Vamsi Gunturu
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Patent number: 11182291Abstract: A computer-implemented method, according to one approach, includes: receiving an I/O request. In response to determining that the I/O request does not include a bypass indication, the I/O request is satisfied using a primary cache which is coupled to a data storage device and a secondary cache having SCM. In response to determining that the data associated with the I/O request has been updated as a result of satisfying the I/O request: the updated data is destaged from the primary cache to the data storage device, the updated data is copied to the secondary cache, and the updated data is demoted from the primary cache. Yet, in response to determining that the data associated with the I/O request has not been updated: the data associated with the I/O request is copied to the secondary cache, and the data associated with the I/O request is demoted from the primary cache.Type: GrantFiled: February 3, 2020Date of Patent: November 23, 2021Assignee: International Business Machines CorporationInventors: Lokesh Mohan Gupta, Edward Hsiu-Wei Lin, Beth Ann Peterson, Matthew G. Borlick
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Patent number: 11175852Abstract: An method of a storage device configured to communicate with an external device through an interface channel includes: storing a throttling predefined table (PDT) including a relationship between target performances and workload characteristics; detecting that a first workload characteristic has changed; determining whether to update the PDT; when it is determined to update the PDT, monitoring a performance of the storage device; updating the PDT to include at least one new value for the workload characteristics and an additional target throttling performance value, based on a calculated monitored performance and the changed value of the first workload characteristic; controlling an operation parameter based on the updated PDT such that the interface channel has a first throttling performance corresponding to the additional target throttling performance value; receiving a first request through the interface channel from the external device; and processing the first I/O request through the interface channel.Type: GrantFiled: July 31, 2020Date of Patent: November 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sangwon Jung, Mincheol Kwon
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Patent number: 11175833Abstract: A method for controlling a data storage device is provided, which includes: upon detecting a use of the device by a user, determining whether the user corresponds to an identifier associated with a first user profile including access rights authorizing at least the writing and reading of data in a memory of the data storage device; if it is determined that the user corresponds to the identifier associated with the first user profile, controlling the use of the data storage device according to the first user profile; and if it is determined that the user does not correspond to the identifier associated with the first user profile, controlling the use of the data storage device according to a second user profile including access rights which permit the writing of data in the memory of the data storage device and which prohibit at least the reading of data, in the memory of the data storage device, that were not previously written by the user.Type: GrantFiled: June 19, 2019Date of Patent: November 16, 2021Assignee: ORANGEInventor: Thierry Gaillet
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Patent number: 11163482Abstract: A method for dynamically altering the performance class of multiple storage drives is disclosed. In one embodiment, such a method monitors, within a storage environment, characteristics (e.g., age, wear, etc.) of multiple storage drives. Each storage drive has a performance class associated therewith. Based on the characteristics, the method periodically modifies the performance class of the storage drives. The method then reorganizes the storage drives within various storage groups (e.g., RAID arrays, storage tiers, workloads, etc.) based on their performance class. For example, the method may place, as much as possible, storage drives of the same performance class within the same storage groups. A corresponding system and computer program product are also disclosed.Type: GrantFiled: June 26, 2019Date of Patent: November 2, 2021Assignee: International Business Machines CorporationInventors: Lokesh M. Gupta, Matthew G. Borlick, Karl A. Nielsen, Micah Robison
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Patent number: 11163500Abstract: Provided is a method for writing and deleting files on a tape medium and a cache storage device. The method includes receiving a command to write one or more files of a directory to a tape medium. The method further includes identifying a cache limit associated with the tape medium. The method further comprises determining whether the amount of data of the directory that is already on the cache storage device exceeds the cache limit. In response to the amount of data not exceeding the cache limit, the method includes writing data of the one or more files to the cache storage device and the tape medium in parallel.Type: GrantFiled: April 26, 2019Date of Patent: November 2, 2021Assignee: International Business Machines CorporationInventors: Tohru Hasegawa, Hiroshi Itagaki, Tsuyoshi Miyamura, Noriko Yamamoto, Shinsuke Mitsuma
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Patent number: 11157198Abstract: Techniques for generating merge-friendly sequential IO patterns in shared logger page descriptor (PD) tiers. The techniques can be employed in an active-active clustered system that includes a primary storage node, a secondary storage node, a logger shared between the primary and secondary storage nodes, and a storage device such as a non-volatile memory (NVM) device. The techniques can include allocating at least a first trunk and a second trunk in a shared PD tier of the logger, sequentially writing PD metadata and/or data by the primary storage node and the secondary storage node to the first trunk and the second trunk, respectively, merging the PD metadata/data units sequentially written to each respective trunk together to obtain PD metadata/data having an increased size up to the size of the respective trunks, and storing the merged PD metadata/data to the NVM device.Type: GrantFiled: March 12, 2020Date of Patent: October 26, 2021Assignee: EMC IP Holding Company LLCInventors: Chun Ma, Socheavy Heng, Geng Han, Hongpo Gao, Shaoqin Gong, Jian Gao
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Patent number: 11157406Abstract: A processing system server and methods for performing asynchronous data store operations. The server includes a processor which maintains a cache of objects in communication with the server. The processor executes an asynchronous computation to determine the value of a first object. In response to a request for the first object occurring before the asynchronous computation has determined the value of the first object, a value of the first object is returned from the cache. In response to a request for the first object occurring after the asynchronous computation has determined the value of the first object, a value of the first object determined by the asynchronous computation is returned. The asynchronous computation may comprise at least one future, such as a ListenableFuture, or at least one process or thread. Execution of an asynchronous computation may occur with a frequency correlated with how frequently the object changes or how important it is to have a current value of the object.Type: GrantFiled: October 31, 2019Date of Patent: October 26, 2021Assignee: International Business Machines CorporationInventor: Arun Iyengar
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Patent number: 11144225Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the same, and more particularly, to a memory system, a memory controller, and a method of operating the same, which calculate a read-attribute value, a write-attribute value, and a time-attribute value for a nonvolatile memory set and determine an operation mode of the nonvolatile memory set on the basis of at least one of the read-attribute value, the write-attribute value, and the time-attribute value, thereby enabling a host to predict whether or not a memory controller executes a background operation.Type: GrantFiled: February 4, 2020Date of Patent: October 12, 2021Assignee: SK hynix Inc.Inventors: Yong-Seok Oh, Hee-Chan Shin, Young-Ho Ahn, Do-Hyeong Lee, Jin-Yeong Kim
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Patent number: 11144244Abstract: A command transmitting method, a memory control circuit unit and a memory storage device are provided. The method includes: transmitting a plurality of command sequences and a state read command sequence to a memory interface coupled to a rewritable non-volatile memory module; and storing the plurality of command sequences by the memory interface, and transmitting the state read command sequence to the rewritable non-volatile memory module.Type: GrantFiled: September 29, 2019Date of Patent: October 12, 2021Assignee: PHISON ELECTRONICS CORP.Inventors: Kuo-Hwa Ho, Chih-Ming Chen
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Patent number: 11144472Abstract: An apparatus and method for managing different page tables for different privilege levels. For example, one embodiment of a processor comprises: a first control register to store a first base address associated with program code executed at a first privilege level; a second control register to store a second base address associated with program code executed at a second privilege level lower than the first privilege level; and address translation circuitry to identify a first base translation table using the first base address responsive to a first address translation request originating from the program code executed at the first privilege level and to identify a second base translation table using the second base address responsive to a second address translation request originating from the program code executed at the second privilege level.Type: GrantFiled: March 27, 2019Date of Patent: October 12, 2021Assignee: INTEL CORPORATIONInventors: Scott Dion Rodgers, Robert S. Chappell, Barry E. Huntley
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Patent number: 11126238Abstract: An open channel solid state drive includes a flash memory including a first block and a controller which controls the flash memory, the controller receiving write data and a physical address of the first block from a host and attempting a write of the data in the first block. The controller generates first data which is not written in the first block among the write data when a power-off occurs during writing attempt. The write data includes the first data and second data already written in the first block. The controller determines whether successive writing of the first data in the first block is possible or impossible. If the successive writing is possible, the controller successively writes the data in the first block. If the successive writing is impossible, the host or the controller writes the first data and the second data in a second block of the flash memory.Type: GrantFiled: September 30, 2019Date of Patent: September 21, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae Ok Kim, In Hae Kang, Min Seok Ko, Yang Woo Roh, In Hwan Doh, Jong Won Lee, Se Jeong Jang
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Patent number: 11126355Abstract: A method, system, and computer program product manages a storage system. Writes to sections in solid state storage devices in endurance tiers in the storage system are monitored by a computer system over a period of time. Responsive to a write rate for the writes to a section in the sections in an current endurance tier in the endurance tiers exceeding a maximum recommended write rate for the current endurance tier during the period of time, data is moved from the section in the current endurance tier to a higher endurance tier in the endurance tiers having a higher maximum recommended write rate than the maximum recommended write rate for the current endurance tier.Type: GrantFiled: February 21, 2020Date of Patent: September 21, 2021Assignee: International Business Machines CorporationInventors: Christopher C. Bode, Nathan B. Best, Abhishek Dhingra
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Patent number: 11119693Abstract: In a method of operating a storage device, a first throughput, for transmitting a plurality of write command completion responses to an external host device, is set to an initial value. The plurality of write command completion responses represent an execution of a plurality of write commands received from the external host device. The plurality of write commands are executed. The plurality of write command completion responses are transmitted to the external host device based on the first throughput that is set to the initial value. A plurality of write data are internally stored based on the plurality of write commands. A second throughput, associated with an operation of internally storing the plurality of write data, is monitored during a predetermined first time interval. The first throughput is changed based on the second throughput that is monitored during the predetermined first time interval.Type: GrantFiled: March 5, 2020Date of Patent: September 14, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sumin Ahn, Jinseok Kim, Jungjeong Jo