Abstract: An analog circuit for solving optimization algorithms comprises three voltage controlled current sources and three capacitors, operatively coupled in parallel to the three voltage controlled current sources, respectively. The circuit further comprises a first inductor, operatively coupled in series between a first pair of the capacitors and the voltage controller current sources and a second pair of the capacitors and the voltage controller current sources. The circuit further comprises a second inductor, operatively coupled in series between the second pair of the capacitors and the voltage controller current sources and a third pair of the capacitors and the voltage controller current sources.

Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. A quasi-delay insensitive (QDI) shift register and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.

Abstract: Embodiments of the present disclosure disclose a method for improving a performance of a pulsed-ultraviolet (PUV) device. The method includes monitoring an input current across a circuit breaker in communication with a UV lamp, where the input current is delivered by a power signal and is interrupted by the circuit breaker upon exceeding a predefined cut-off current; generating a pulse signal having a set of frequencies based on the power signal for driving the UV lamp, where the pulse signal is associated with a predetermined cut-off frequency that increases the input current beyond the cut-off current; determining a predefined threshold current less than the cut-off current; and configuring the pulse signal with multiple distinct pulse frequencies per second for a predefined configuration period based on the input current exceeding the threshold current. The distinct pulse frequencies per second include at least one pulse frequency greater than the cut-off frequency.

Abstract: A system and method for a logic device is disclosed. A first nanotrack along a first axis and a second nanotrack along a second axis perpendicular to the first axis are disposed over a substrate. The second nanotrack is disposed over the first nanotrack in a overlap portion. An input value is defined about a first end of the first nanotrack and the second nanotrack by nucleating a skyrmion, wherein a presence of the skyrmion defines a first value and absence of the skyrmion defines a second value. The nucleated skyrmion moves towards the second end of the nanotracks when a charge current is passed through the first nanotrack and the second nanotrack along the second axis. The presence of the skyrmion sensed at the second end of the nanotrack indicates an output value of the first value.

Abstract: A combined logic control circuit and a sewage treatment system are provided. The combined logic control circuit includes: at least one signal input component, a control component and at least one signal output component; each signal input component transmits at least one path of first communication signal in a photoelectric isolated manner and converts the first communication signal into a second communication signal; the control component generates at least one path of first control signal according to the at least one path of second communication signal; and each signal output component processes one path of the first control signal to control at least one external electrical device, thereby implementing a particular circuit function; and the power switch component provides power supply to the various circuit components in a photoelectric isolated manner.

Abstract: The present disclosure relates to a composite logic gate circuit, including: a simple logic gate circuit including a first logic gate circuit and an inverter circuit, a first PMOS transistor, and a first NMOS transistor. The first logic gate circuit is configured to receive a first input signal and a second input signal, and to output a first output signal. The inverter circuit includes a second PMOS transistor and a second NMOS transistor. A source of the second PMOS transistor is coupled to a power input terminal, a drain is coupled to a drain of the second NMOS transistor, and a gate is configured to receive the first output signal. A source of the second NMOS transistor is coupled to a ground terminal, and a gate is configured to receive the first output signal. A source of the first PMOS transistor is coupled to the drain of the second PMOS transistor, a drain is coupled to a drain of the first NMOS transistor, and a gate is configured to receive a third input signal.

Abstract: A method includes obtaining a plurality of entangled qubits, with high fault tolerance, represented by a lattice structure. The lattice structure includes a plurality of contiguous lattice cells. A first subset of the plurality of entangled qubits defines a first plane, and a second subset of the plurality of entangled qubits defines a second plane that is parallel to and offset from the first plane. The plurality of entangled qubits includes a defect qubit that is entangled with at least one face qubit on the first plane and at least one edge qubit on the second plane.

Abstract: A combinational logic circuit includes input circuitry to receive a first and second input signals that transition between supply voltages of first and second voltage domain, respectively. The input circuitry generates, based on the first and second input signals, a first internal signal that transitions between one of the supply voltages of the first voltage domain and one of the supply voltages of the second voltage domain. Output circuitry within the combinational logic circuit generates an output signal that transitions between the upper and lower supply voltages of the first voltage domain in response to transition of the first internal signal.

Abstract: Methods, systems, and apparatus for performing phase operations. In one aspect, a method for performing a same phase operation on a first and second qubit using a third qubit prepared in a phased plus state includes: performing a first NOT operation on the third qubit; computing a controlled adder operation on the first, second and third qubit, comprising encoding the result of the controlled adder operation in a fourth qubit; performing a square of the phase operation on the fourth qubit; uncomputing the controlled adder operation on the first, second and third qubit; performing a CNOT operation between the first qubit and the third qubit, wherein the first qubit acts as the control; performing a CNOT operation between the second qubit and the third qubit, wherein the second qubit acts as the control; and performing a second NOT operation on the third qubit.

Abstract: The remote control device may provide feedback via the status indicator that indicates the present intensity level of a lighting device responsive to the remote control device. The remote control device may provide feedback to indicate a first present intensity level of a first lighting device when the command is a first command type, and a second present intensity level of a second lighting device when the command is a second command type. When the first command type is a raise command and the second command type is a lower command, the first present intensity level may be less than the second present intensity level. In addition, the first lighting device may be a lighting device responsive to the remote control device with a lowest present intensity level and the second lighting device may be a lighting device responsive to the remote control device with a highest present intensity level.

Abstract: A method of routing interconnects of a field programmable gate array including: a plurality of logic tiles, and a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects to interconnect logic tile networks of the logic tiles, the method comprises: routing a first plurality of tile-to-tile interconnects in a first plurality of logic tiles. After routing the first plurality of tile-to-tile interconnects, routing a second plurality of tile-to-tile interconnects in a second plurality of logic tiles. The start/end point of each tile-to-tile interconnect in the first plurality and the second plurality of tiles is independent of the start/end point of the other tile-to-tile interconnects in the first and second plurality, respectively.

Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.

Abstract: An integrated circuit is provided, including a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits multiple data signals to the second latch circuit through multiple first conductive lines disposed on a front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through multiple second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.

Abstract: In an embodiment, a method includes programming a control signal that specifies a target resistance and a target voltage in a circuit. The method further includes sending the control signal to at least one transistor configured to control a current flow in the circuit. The method further includes providing, as an output, a signal with the target voltage and target resistance.

Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.

Abstract: An integrated circuit device includes a programmable logic fabric that has programmable logic circuitry and a partial reconfiguration region. The integrated circuit device also includes a network-on-chip formed in soft logic of the integrated circuit device. Additionally, the network-on-chip is configurable to remain operable during a partial reconfiguration of the partial reconfiguration region.

Abstract: An integrated circuit (“IC”) module includes a substrate, multiple field-programmable gate array (“FPGA”) dies, and pads capable of being selectively configured to perform one or more user defined logic functions. The substrate is configured to house multiple FPGA dies side-by-side in an array formation facilitating transmission of signals between the FPGA dies or chips. The FPGA dies are placed on the substrate functioning as a single FPGA device. The periphery dies of the FPGA dies are configured for external connectivity and the interior dies which are interconnected to perform user defined logic functions. The pads, in one aspect, coupling to the FPGA dies, are configured to provide connections between at least some of the FPGA dies.

Abstract: A method includes receiving a selection signal from a third-party device and a status signal from the third-party device. A data signal from the third-party device is latched when both the selection signal and the status signal are active. In addition, a second selection signal and a second status signal can be received from a second third-party device and a second data signal latched when both the second selection signal and the second status signal are active.

Abstract: A circuit including: a transistor, a base of the transistor being switchably connectable to a signal source; and a first diode connected between the base and a reference voltage. The circuit is arranged such that when the signal source is not connected to the base of the transistor, a voltage applied at an emitter of the transistor causes a current flow through the base of the transistor and through the first diode such that the transistor is in an ON state, and when the signal source is connected to the base of the transistor, current flow through the base reduces such that the transistor switches to an OFF state. The circuit includes a second diode, and the signal source is connectable to the base of the transistor through the second diode.

Abstract: An integrated circuit according to one or more embodiments may include a terminal to which an impedance element and a power supply having a predetermined potential can be connected. The integrated circuit may be configured to change a potential of one of electrodes of the impedance element connected to the terminal, detect a change in electrical characteristics of the terminal based on characteristics of the impedance element when the potential of the one electrode of the impedance element is changed, to determine a setting condition among a plurality of setting conditions that are used for an operation of the integrated circuit, store the setting condition in a storage, and use the setting condition stored in the storage for the operation of the integrated circuit.