Abstract: The present invention discloses an ultra-wideband cross-polarized antenna and ultra-wideband cross-polarized array antenna, including a substrate, and a first polarized antenna and a second polarized antenna provided in the substrate and orthogonal to each other. The ultra-wideband cross-polarized antenna has a simple structure, is easy to produce and is able to solve challenging bandwidth issues, cross-polarized port isolation issues, and beam scanning range issues in 5G millimeter wave array antennas.

Abstract: A method of generating light settings for a plurality of lighting units, the method comprising obtaining one or more images, extracting a plurality of colors from the one or more images, selecting a subset of colors from the plurality of colors, wherein the subset of colors is selected based on a target time of day, and generating one or more light settings for the plurality of lighting units based on the selected subset of colors, wherein, when the one or more light settings are activated, the plurality of lighting units are controlled according to the subset of colors.

Abstract: A semiconductor product being convertible or converted from a customizable configuration into a selectable or selected one of a plurality of different customized configurations, wherein the semiconductor product comprises a customizing unit configured for customizing the semiconductor product into one of the customized configurations selected by a received customizing data structure specifying a selected application of the semiconductor product, and a plurality of functional blocks each configured for providing an assigned functionality and all being deactivated when the semiconductor product is not in one of the customized configurations, wherein the customizing unit is configured for activating only a subgroup of the functional blocks based on the received customizing data structure.

Abstract: The present disclosure describes various aspects of complementary 2(N)-bit redundancy for single event upset (SEU) prevention. In some aspects, an integrated circuit includes a data storage element to store a data value, another data storage element to store a complementary data value, a multi-bit data storage element (e.g., a 2-bit storage element) to store both the data value and the complementary data value, and voting logic that may enable a complementary data storage scheme with inter-circuit redundancy to prevent SEU. Additionally, the voting logic of the integrated circuit may enable detection and correction of data value errors and/or enable programming of voting logic criteria, which may be implemented dynamically based on a type of SEU failures that are detected or corrected.

Abstract: An integrated circuit die includes input buffer circuits that are enabled during an input mode of operation in response to first control signals to transmit input signals into the integrated circuit die from conductive bumps. Each of the input buffer circuits is coupled to one of the conductive bumps. The integrated circuit die also includes output buffer circuits that are each coupled to one of the conductive bumps. The output buffer circuits are enabled during an output mode of operation in response to second control signals to transmit output signals from the integrated circuit die to the conductive bumps. The input buffer circuits are disabled from transmitting signals during the output mode of operation in response to the first control signals. The output buffer circuits are disabled from transmitting signals during the input mode of operation in response to the second control signals.

Abstract: Apparatus and associated methods relate to quasi-adiabatic logic gates in which at least one supply terminal receives a periodic power signal. The quasi-adiabatic logic gate is configured to perform a specific logic function operative upon one or more input signals. When the quasi-adiabatic logic gate switches the output from one logic state to another logic state, the transient switching portion of the output signal substantially tracks the periodic supply signal. Such a periodic supply signal can be one that transitions gradually between low and high voltage levels. Such periodic supply signals results in a transient switching portion of the logic signal having lower frequency components than have traditional CMOS logic gate transients. The quasi-adiabatic logic gate has a periodic clock signal that is not in phase with the periodic power signal.

Abstract: A calibration system is disclosed. The calibration system includes a waveform generator configured to generate a periodic waveform and a control circuit in signal communication with the waveform generator. The control circuit includes an analog-to-digital converter configured to convert the periodic waveform to digital values and an electronic device in signal communication with the analog-to-digital converter. The electronic device is configured to verify calibration of (1) timing of the control circuit and (2) voltage levels of the control circuit based on the periodic waveform.

Abstract: A logic process-based level conversion circuit of a flash flash field programmable gate array (FPGA) performs three-stage level conversion by using three conversion modules. A first-stage conversion module is configured to convert an input first signal of a VDD-GND voltage domain into a second signal of a VP1-GND voltage domain, an intermediate-stage conversion module is configured to convert the input second signal of the VP1-GND voltage domain into a third signal of a VP1-VN voltage domain, and a drive-stage conversion module is configured to convert the input third signal of the VP1-VN voltage domain into a drive signal of a VP2-VN voltage domain and output a drive word line. The logic process-based level conversion circuit reduces the pressure of conversion at each stage, ensures a capability of driving the next stage, increases the conversion speed, and provides a large driving capability at the last stage.

Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.

Abstract: An antenna module according to an embodiment of the present disclosure enables the size of a wireless communication terminal to be reduced by the implementation, as a first antenna formed by an MID method and a second antenna formed on an FPCB, of the antenna module used in the wireless communication terminal. The antenna module is capable of performing a plurality of communication functions through a single antenna module by enabling the first antenna to function as a near-field communication (NFC) antenna and the second antenna to function as a magnetic secure transmission (MST) antenna.

Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.

Abstract: Provided are a reconfigurable processor and a reconfigurable processor system, where the reconfigurable processor includes: a hardware message management module (110), a memory management system (120) and an arithmetic and logic unit (130). The memory management system (120) is connected to the hardware message management module (110) and the arithmetic and logic unit (130) respectively; the hardware message management module (110) is configured to read and parse at least one hardware message, to configure a priority of each of the at least one hardware message and store each of the at least one hardware message into a memory through the memory management system (120); and the arithmetic and logic unit (130) is configured to run the at least one hardware message according to the configured priority.

Abstract: An antenna and a detecting device are provided. The antenna includes a ground plane, a pole and a microstrip line. The detecting device includes an oscilloscope and the antenna that is connected with the oscilloscope.

Abstract: A Field Programmable Gate Array (FPGA) system includes a main FPGA and one or more sub-FPGAs connected to the main FPGA. The main FPGA is configured to detect a positive edge of a pulse included in a user clock using a sampling clock of the main FPGA, generate a flag using the detected positive edge, generate a clock packet indicating the generated flag, and provide the generated clock packet to any one of the one or more sub-FPGAs.

Abstract: Provided is a phase self-correction circuit, including a trigger signal operation module and a signal phase correction module. The trigger signal operation module and the signal phase correction module are both composed of a plurality of discrete components. The trigger signal operation module is configured to perform a logical operation on an input phase standard reference signal and actual transmission signal, to obtain a target trigger signal for triggering the signal phase correction module; and the signal phase correction module is configured to output, based on trigger modes of the target trigger signal and the actual transmission signal, a self-correction transmission signal with the same waveform as that of the phase standard reference signal, to realize phase self-correction on the actual transmission signal.

Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.

Abstract: In a general aspect, calibration is performed in a quantum computing system. In some cases, domains of a quantum computing system are identified, where the domains include respective domain control subsystems and respective subsets of quantum circuit devices in a quantum processor of the quantum computing system. Sets of measurements are obtained from one of the domains and stored in memory. Device characteristics of the quantum circuit devices of the domain are obtained based on the set of measurements, and the device characteristics are stored in a memory of the control system. Quantum logic control parameters for the subset of quantum circuit devices of the domain are obtained based on the set of measurements and stored in memory.

Abstract: An antenna device (10) includes a substrate (100) including a first surface (102), a first antenna (200) provided on the substrate (100), a second antenna (300) provided on the substrate (100), and a third antenna (400) provided on the first surface (102) of the substrate (100), and a center point (CP) of the third antenna (400) is positioned on the same side as an end portion (EP2) of the second antenna (300) furthest from the first antenna (200), relative to a center line (CL) passing through a center of a line (L) connecting an end portion (EP1) of the first antenna (200) furthest from the second antenna (300) and the end portion (EP2) of the second antenna (300) furthest from the first antenna (200), or relative to a center line (CL) of the first surface (102) of the substrate (100).

Abstract: A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.

Abstract: An analog circuit for solving optimization algorithms comprises three voltage controlled current sources and three capacitors, operatively coupled in parallel to the three voltage controlled current sources, respectively. The circuit further comprises a first inductor, operatively coupled in series between a first pair of the capacitors and the voltage controller current sources and a second pair of the capacitors and the voltage controller current sources. The circuit further comprises a second inductor, operatively coupled in series between the second pair of the capacitors and the voltage controller current sources and a third pair of the capacitors and the voltage controller current sources.