Patents Examined by Jany Richardson
  • Patent number: 12015402
    Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: June 18, 2024
    Assignee: Kepler Computing Inc.
    Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
  • Patent number: 12015404
    Abstract: A logic process-based level conversion circuit of a flash flash field programmable gate array (FPGA) performs three-stage level conversion by using three conversion modules. A first-stage conversion module is configured to convert an input first signal of a VDD-GND voltage domain into a second signal of a VP1-GND voltage domain, an intermediate-stage conversion module is configured to convert the input second signal of the VP1-GND voltage domain into a third signal of a VP1-VN voltage domain, and a drive-stage conversion module is configured to convert the input third signal of the VP1-VN voltage domain into a drive signal of a VP2-VN voltage domain and output a drive word line. The logic process-based level conversion circuit reduces the pressure of conversion at each stage, ensures a capability of driving the next stage, increases the conversion speed, and provides a large driving capability at the last stage.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: June 18, 2024
    Assignee: WUXI ESIONTECH CO., LTD.
    Inventors: Zhengzhou Cao, Yueer Shan, Zhenkai Ji, Jing Sun, Chunyan He, Guangming Li
  • Patent number: 12013435
    Abstract: A calibration system is disclosed. The calibration system includes a waveform generator configured to generate a periodic waveform and a control circuit in signal communication with the waveform generator. The control circuit includes an analog-to-digital converter configured to convert the periodic waveform to digital values and an electronic device in signal communication with the analog-to-digital converter. The electronic device is configured to verify calibration of (1) timing of the control circuit and (2) voltage levels of the control circuit based on the periodic waveform.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: June 18, 2024
    Assignee: Westinghouse Electric Company LLC
    Inventors: Timothy S. Meyers, Daniel G. Gruber, Mark A. Bartels, Kenneth J. Swidwa
  • Patent number: 12009587
    Abstract: An antenna module according to an embodiment of the present disclosure enables the size of a wireless communication terminal to be reduced by the implementation, as a first antenna formed by an MID method and a second antenna formed on an FPCB, of the antenna module used in the wireless communication terminal. The antenna module is capable of performing a plurality of communication functions through a single antenna module by enabling the first antenna to function as a near-field communication (NFC) antenna and the second antenna to function as a magnetic secure transmission (MST) antenna.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: June 11, 2024
    Assignee: KESPION CO., LTD.
    Inventors: Hee Su Kim, Gwan Woo Son, Won Ro Lee
  • Patent number: 12009820
    Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: June 11, 2024
    Assignee: Kepler Computing Inc.
    Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
  • Patent number: 12001381
    Abstract: Provided are a reconfigurable processor and a reconfigurable processor system, where the reconfigurable processor includes: a hardware message management module (110), a memory management system (120) and an arithmetic and logic unit (130). The memory management system (120) is connected to the hardware message management module (110) and the arithmetic and logic unit (130) respectively; the hardware message management module (110) is configured to read and parse at least one hardware message, to configure a priority of each of the at least one hardware message and store each of the at least one hardware message into a memory through the memory management system (120); and the arithmetic and logic unit (130) is configured to run the at least one hardware message according to the configured priority.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: June 4, 2024
    Assignee: MORNINGCORE TECHNOLOGY CO., CHINA
    Inventor: Weibing Wang
  • Patent number: 11996619
    Abstract: An antenna and a detecting device are provided. The antenna includes a ground plane, a pole and a microstrip line. The detecting device includes an oscilloscope and the antenna that is connected with the oscilloscope.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: May 28, 2024
    Assignee: QATAR FOUNDATION FOR EDUCATION, SCIENCE AND COMMUNITY DEVELOPMENT
    Inventors: Ahmad Darwish, Shady S. Khalil, Haitham Abu-Rub, Hamid Toliyat
  • Patent number: 11990904
    Abstract: A Field Programmable Gate Array (FPGA) system includes a main FPGA and one or more sub-FPGAs connected to the main FPGA. The main FPGA is configured to detect a positive edge of a pulse included in a user clock using a sampling clock of the main FPGA, generate a flag using the detected positive edge, generate a clock packet indicating the generated flag, and provide the generated clock packet to any one of the one or more sub-FPGAs.
    Type: Grant
    Filed: December 20, 2023
    Date of Patent: May 21, 2024
    Assignee: REBELLIONS INC.
    Inventors: Kyeongryeol Bong, Juyeong Yoon
  • Patent number: 11977956
    Abstract: In a general aspect, calibration is performed in a quantum computing system. In some cases, domains of a quantum computing system are identified, where the domains include respective domain control subsystems and respective subsets of quantum circuit devices in a quantum processor of the quantum computing system. Sets of measurements are obtained from one of the domains and stored in memory. Device characteristics of the quantum circuit devices of the domain are obtained based on the set of measurements, and the device characteristics are stored in a memory of the control system. Quantum logic control parameters for the subset of quantum circuit devices of the domain are obtained based on the set of measurements and stored in memory.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: May 7, 2024
    Assignee: Rigetti & Co, LLC
    Inventors: Benjamin Jacob Bloom, Shane Arthur Caldwell, Michael James Curtis, Matthew J. Reagor, Chad Tyler Rigetti, Eyob A. Sete, William J. Zeng, Peter Jonathan Karalekas, Nikolas Anton Tezak, Nasser Alidoust
  • Patent number: 11979153
    Abstract: A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: May 7, 2024
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Jean-Francois Link, Mark Wallis, Joran Pantel
  • Patent number: 11979149
    Abstract: Provided is a phase self-correction circuit, including a trigger signal operation module and a signal phase correction module. The trigger signal operation module and the signal phase correction module are both composed of a plurality of discrete components. The trigger signal operation module is configured to perform a logical operation on an input phase standard reference signal and actual transmission signal, to obtain a target trigger signal for triggering the signal phase correction module; and the signal phase correction module is configured to output, based on trigger modes of the target trigger signal and the actual transmission signal, a self-correction transmission signal with the same waveform as that of the phase standard reference signal, to realize phase self-correction on the actual transmission signal.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: May 7, 2024
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Jie Liu, Xu Wang
  • Patent number: 11979148
    Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: May 7, 2024
    Assignee: Kepler Computing Inc.
    Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
  • Patent number: 11978970
    Abstract: An antenna device (10) includes a substrate (100) including a first surface (102), a first antenna (200) provided on the substrate (100), a second antenna (300) provided on the substrate (100), and a third antenna (400) provided on the first surface (102) of the substrate (100), and a center point (CP) of the third antenna (400) is positioned on the same side as an end portion (EP2) of the second antenna (300) furthest from the first antenna (200), relative to a center line (CL) passing through a center of a line (L) connecting an end portion (EP1) of the first antenna (200) furthest from the second antenna (300) and the end portion (EP2) of the second antenna (300) furthest from the first antenna (200), or relative to a center line (CL) of the first surface (102) of the substrate (100).
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: May 7, 2024
    Assignee: YOKOWO CO., LTD.
    Inventors: Kazuya Matsunaga, Takeshi Sampo, Yuki Kikuchi
  • Patent number: 11967951
    Abstract: An analog circuit for solving optimization algorithms comprises three voltage controlled current sources and three capacitors, operatively coupled in parallel to the three voltage controlled current sources, respectively. The circuit further comprises a first inductor, operatively coupled in series between a first pair of the capacitors and the voltage controller current sources and a second pair of the capacitors and the voltage controller current sources. The circuit further comprises a second inductor, operatively coupled in series between the second pair of the capacitors and the voltage controller current sources and a third pair of the capacitors and the voltage controller current sources.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: April 23, 2024
    Assignee: Xerox Corporation
    Inventors: Ion Matei, Aleksandar Feldman, Johan de Kleer
  • Patent number: 11960734
    Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. A quasi-delay insensitive (QDI) shift register and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: April 16, 2024
    Assignee: Intel Corporation
    Inventors: Sean R Atsatt, Ilya K. Ganusov
  • Patent number: 11955973
    Abstract: A system and method for a logic device is disclosed. A first nanotrack along a first axis and a second nanotrack along a second axis perpendicular to the first axis are disposed over a substrate. The second nanotrack is disposed over the first nanotrack in a overlap portion. An input value is defined about a first end of the first nanotrack and the second nanotrack by nucleating a skyrmion, wherein a presence of the skyrmion defines a first value and absence of the skyrmion defines a second value. The nucleated skyrmion moves towards the second end of the nanotracks when a charge current is passed through the first nanotrack and the second nanotrack along the second axis. The presence of the skyrmion sensed at the second end of the nanotrack indicates an output value of the first value.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: April 9, 2024
    Assignee: CEREMORPHIC, INC.
    Inventors: Akshaykumar Salimath, Sanghamitra Debroy, Venkat Mattela
  • Patent number: 11955303
    Abstract: Embodiments of the present disclosure disclose a method for improving a performance of a pulsed-ultraviolet (PUV) device. The method includes monitoring an input current across a circuit breaker in communication with a UV lamp, where the input current is delivered by a power signal and is interrupted by the circuit breaker upon exceeding a predefined cut-off current; generating a pulse signal having a set of frequencies based on the power signal for driving the UV lamp, where the pulse signal is associated with a predetermined cut-off frequency that increases the input current beyond the cut-off current; determining a predefined threshold current less than the cut-off current; and configuring the pulse signal with multiple distinct pulse frequencies per second for a predefined configuration period based on the input current exceeding the threshold current. The distinct pulse frequencies per second include at least one pulse frequency greater than the cut-off frequency.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: April 9, 2024
    Assignee: Anram Holdings
    Inventors: Prakash Valentino Ramanand, Manjinder Singh Dhillon
  • Patent number: 11955968
    Abstract: A combined logic control circuit and a sewage treatment system are provided. The combined logic control circuit includes: at least one signal input component, a control component and at least one signal output component; each signal input component transmits at least one path of first communication signal in a photoelectric isolated manner and converts the first communication signal into a second communication signal; the control component generates at least one path of first control signal according to the at least one path of second communication signal; and each signal output component processes one path of the first control signal to control at least one external electrical device, thereby implementing a particular circuit function; and the power switch component provides power supply to the various circuit components in a photoelectric isolated manner.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: April 9, 2024
    Assignee: YUNNAN HEXU ENVIRONMENTAL TECHNOLOGY CO., LTD.
    Inventors: Wensheng Li, Jingguo Ding, Jiesheng Luo, Ranrong Liu
  • Patent number: 11949416
    Abstract: The present disclosure relates to a composite logic gate circuit, including: a simple logic gate circuit including a first logic gate circuit and an inverter circuit, a first PMOS transistor, and a first NMOS transistor. The first logic gate circuit is configured to receive a first input signal and a second input signal, and to output a first output signal. The inverter circuit includes a second PMOS transistor and a second NMOS transistor. A source of the second PMOS transistor is coupled to a power input terminal, a drain is coupled to a drain of the second NMOS transistor, and a gate is configured to receive the first output signal. A source of the second NMOS transistor is coupled to a ground terminal, and a gate is configured to receive the first output signal. A source of the first PMOS transistor is coupled to the drain of the second PMOS transistor, a drain is coupled to a drain of the first NMOS transistor, and a gate is configured to receive a third input signal.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: April 2, 2024
    Assignee: SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Weixin Kong, Dong Yu, Wenbo Tian, Zhijun Fan, Zuoxing Yang
  • Patent number: 11941488
    Abstract: Methods, systems, and apparatus for performing phase operations. In one aspect, a method for performing a same phase operation on a first and second qubit using a third qubit prepared in a phased plus state includes: performing a first NOT operation on the third qubit; computing a controlled adder operation on the first, second and third qubit, comprising encoding the result of the controlled adder operation in a fourth qubit; performing a square of the phase operation on the fourth qubit; uncomputing the controlled adder operation on the first, second and third qubit; performing a CNOT operation between the first qubit and the third qubit, wherein the first qubit acts as the control; performing a CNOT operation between the second qubit and the third qubit, wherein the second qubit acts as the control; and performing a second NOT operation on the third qubit.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: March 26, 2024
    Assignee: Google LLC
    Inventor: Craig Gidney