Abstract: A transceiver includes a transmitter and a receiver coupled to each other through a first line and a second line. The transmitter transmits a first voltage signal of a second logic level or a fourth logic level, among a first logic level, the second logic level, a third logic level, and the fourth logic level, through the first line. The transmitter transmits a second voltage signal of the first logic level or the third logic level through the second line. The receiver generates an output signal having one of four values based on the first voltage signal and the second voltage signal.

Abstract: The present application provides an output driving circuit and a memory. The output driving circuit includes: a signal input terminal inputting a positive input signal and a negative input signal complementary to each other; a pull-up output unit and a pull-down output unit connected to the signal input terminal, the positive input signal acting as an input signal of the pull-up output unit, and the negative input signal acting as an input signal of the pull-down output unit; at least one compensation unit connected in parallel with the pull-up or pull-down output unit; at least one pulse signal generation circuit, and generating a pulse signal, the pulse signal acting as a control signal of the compensation unit; and a signal output terminal connected to an output terminal of the pull-up output unit, an output terminal of the pull-down output unit and an output terminal of the compensation unit.

Abstract: A table-based state machine is improved by reducing critical dependence path. In one aspect, all current states for a given input are read from a state table circuit, and the next state and output are then selected therefrom by an output multiplexer based on the current state, removing dependence on the current state from the table read, and allowing the read(s) to be pipelined. In a further aspect, multiple input units are configured to operate on multiple inputs in parallel, with each input unit propagating its state table circuit for its current input to the next downstream input unit. Each downstream input unit is configured to use the propagated state table circuit to provide the state table circuit reads to the proper output multiplexer input. The number of possible output states for a given input may be dynamically reduced, reducing the size of the output multiplexer selecting the next state.

Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.

Abstract: A semiconductor device that can perform product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits; the first circuit includes a first holding node and the second circuit includes a second holding node. The first circuit is electrically connected to first and second input wirings and first and second wirings, the second circuit is electrically connected to the first and second input wirings and the first and second wirings, and the first and second circuits each have a function of holding first and second potentials corresponding to first data at the first and second holding nodes. When a potential corresponding to second data is input to each of the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring.

Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.

Abstract: A mobile device that is configured for wireless communication may be configured to operate as a remote control device in a lighting control system, controlling one or more lighting control devices of the lighting control system. The remote control device may control the light intensity in a space, for instance at a location of the remote control device, in response to an ambient light intensity measured at the remote control device. The remote control device may define a user interface for receiving an input that indicates a desired light intensity at the location. The remote control device may measure the ambient light intensity at the location via a light detector, compare the measured ambient light intensity to the desired light intensity, and cause the one or more lighting control devices to adjust the ambient light intensity at the remote control device until it agrees with the desired light intensity.

Abstract: An integrated circuit for use in high-reliability electronic systems contains one or more digital majority voters with corresponding disagreement detectors connected to the same input signals producing a majority value output and an error signal that is active when not all input signals agree. Internal error signals from multiple majority voter/disagreement detectors as well as external error inputs may be combined using disjunctive error logic to produce an “error detected” output indication. Cold-sparing and hot-plugging are supported by providing cold-sparable electrostatic discharge protection circuits and power-on reset circuitry controlling cold-sparable output stages. Internal modular redundancy provides immunity to single-event transients as well as enhanced reliability.

Abstract: A wake-up circuit, a wake-up method and a non-transitory computer-readable storage medium are disclosed. The wake-up circuit includes a wake-up module (11) and a main control module (12). The wake-up module (11) is connected to a wake-up source and is configured to detect a wake-up signal sent by the wake-up source, and to forward the wake-up signal to the main control module (12), one or more wake-up sources being provided. The main control module (12) is connected to the wake-up module (11) and is configured to receive the forwarded wake-up signal, one main control modules (12) being provided.

Abstract: An antenna unit includes a coupling element including first and second coils, a feeding radiating element, and a parasitic radiating element. A series circuit including the first coil and a feeder circuit is connected to the feeding radiating element, and the parasitic radiating element is connected to the second coil. A distance between open ends of the parasitic radiating element and a short portion of the feeding radiating element is shorter than a distance between open ends of the parasitic radiating element and a long portion the feeding radiating element. The antenna unit is an antenna for a first frequency band with fundamental wave resonance of the long portion and fundamental wave resonance of the parasitic radiating element, and a second frequency band with higher-order resonance of the parasitic radiating element and resonance of the short portion, the second frequency band being higher than the first frequency band.

Abstract: This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (PRO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (PRST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (VPB1, VPB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

Abstract: A control module attached to a lighting fixture and having a front cover portion may comprise one or more sensors, such as a daylight and/or occupancy sensor, for sensing information through the front cover portion. The control module may have a main printed circuit board (PCB) that extends from a front side to a rear side of the control module, and a sensor PCB perpendicular to the main PCB to enable at least one sensor attached to the sensor PCB to face the front side of the control module. The main PCB may comprise a wireless communication circuit and an antenna for communicating radio frequency (RF) signals, wherein at least a portion of the antenna is located within a plastic lip of the front cover portion of the control module. The control module may further have a conductive enclosure to reduce radio-frequency interference noise from coupling into the antenna.

Abstract: A matching network for a system having a non-linear load and powered by a first RF power supply operating at a first frequency and a second RF power supply operating at a second frequency. The matching network includes a first matching network section for providing an impedance match between the first power supply and the load. The matching network also includes a second matching network section for providing an impedance match between the second power supply and the load. The first matching network section includes a first variable reactance, and the variable reactance is controlled in accordance with IMD sensed in the signal applied to the load by the first RF power supply. The variable reactance is adjusted in accordance with the IMD to reduce the detected IMD.

Abstract: A method for operating an integrated circuit chip including multiple tiles (202a-202d) includes determining a configuration for the tiles for execution of a computation. When the configuration for the tiles satisfies a first criterion, the integrated circuit is operated in a first mode, including concurrently receiving respective input data (208a, 208b) at each of the tiles (202a-202d).

Abstract: A selection circuit, a method for controlling the selection circuit, and a multiplexing circuit are provided. The selection circuit includes N control circuits and M booster circuits. Control terminals of M control circuits among the N control circuits are coupled to output terminals of the M booster circuits, respectively, and first input terminals of the M booster circuits are coupled to receive M control signals among N control signals, respectively. Second input terminals of the M booster circuits are coupled to receive M boost signals respectively, and each booster circuit is configured to provide the received control signal to an output terminal of the booster circuit and increase a potential at the output terminal of the booster circuit by using the received boost signal.

Abstract: In some embodiments, an antenna module includes an antenna element having a first side and a second side opposite the first side, the first side comprising a radiating side of the antenna element and a support structure disposed at the second side of the antenna element and configured to define a cavity, the support structure including a portion configured to reduce signal leakage between the antenna element and the cavity.

Abstract: The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.

Abstract: An integrated circuit (IC) includes an Input/Output (I/O) interface, first-domain circuitry and second-domain circuitry. The I/O interface is coupled to a first voltage domain and is configurable by a set of control bits. The second-domain circuitry is coupled to a second voltage domain and is configured to generate a bit value for a control bit among the control bits, to generate a multi-bit identifier (ID) of the control bit, and to transmit the bit value and the multi-bit ID. The first-domain circuitry is coupled to the first voltage domain and is configured to receive the bit value and the multi-bit ID, to identify the control bit from the multi-bit ID, and to configure the control bit of the I/O interface with the bit value.

Abstract: Provided are a programmable device for processing a data set, and a method for processing a data set. The programmable device includes a plurality of accumulation circuits, wherein each of the accumulation circuits includes a pipeline adder and a cache unit for storing a computation result of the pipeline adder; and a multiplexer for receiving in sequence data in a data set, dynamically determining a correlation between a plurality of features included in the data and the plurality of accumulation circuits, and respectively sending, according to the correlation, feature values of the plurality of features in the received data to corresponding accumulation circuits.

Abstract: A parasitic-aware single-edge triggered flip-flop reduces clock power through layout optimization, enabled through process-circuit co-optimization. The static pass-gate master-slave flip-flop utilizes novel layout optimization enabling significant power reduction. The layout removes the clock poly over notches in the diffusion area. Poly lines implement clock nodes. The poly lines are aligned between n-type and p-type active regions.