Abstract: Methods and systems are provided for configuring static memory in a device by analyzing a set of functionalities of a first device based on at least one use case wherein the at least one use case are associated with configuring available static memory in processing at least one functionality of the first device; configuring at least a first profile composed of the first part for memory allocation of the available static memory to a first processor, and a second part for memory allocation of the available static memory to a second processor of the first device; selecting the first profile either automatically or via a graphical user interface (GUI) by identifying a set of performance characteristics related to the functionality, and implementing the memory allocation by the first profile in processing the at least one functionality in the use case by the first device.

Abstract: A plurality of memory device life metrics are determined, where one of the plurality of memory device life metrics comprises a read count metric that specifies a number of read operations performed on the memory device. A plurality of normalized metric values are calculated, where each of the normalized metric values is based on a ratio of a respective memory device life metric to a respective lifetime target value associated with the respective memory device life metric. A normalized metric value that satisfies a selection criterion is identified from the plurality of normalized metric values. The identified normalized metric value corresponds to an amount of used device life of the memory device. An amount of remaining device life of the memory device is determined based on the identified normalized metric value. An indication of the amount of remaining device life is provided to a host system.

Abstract: A storage system includes a plurality of storage devices. Each of the plurality of storage devices includes a nonvolatile memory device, a buffer memory and a memory controller that controls the nonvolatile memory device and the buffer memory. At least one storage device of the plurality of storage devices is a computational storage device. The computational storage device further includes a storage controller that performs a computational operation for controlling the storage system.

Abstract: An approach provides indirect addressing support for PIM. Indirect PIM commands include address translation information that allows memory modules to perform indirect addressing. Processing logic in a memory module processes an indirect PIM command and retrieves, from a first memory location, a virtual address of a second memory location. The processing logic calculates a corresponding physical address for the virtual address using the address translation information included with the indirect PIM command and retrieves, from the second memory location, a virtual address of a third memory location. This process is repeated any number of times until one or more indirection stop criteria are satisfied. The indirection stop criteria stop the process when work has been completed normally or to prevent errors. Implementations include the processing logic in the memory module working in cooperation with a memory controller to perform indirect addressing.

Abstract: The present application relates to a garbage collection method and a storage device for reducing write amplification. A method for selecting a data block to be collected in garbage collection, including: obtaining, according to a first selection policy, a first data block to be collected; determining, according to a first rejection policy, whether to refuse to collect the first data block to be collected; and if according to the first rejection policy, rejection to collect of the first data block to be collected is determined, not performing garbage collection on the first data block to be collected.

Abstract: A host server computer with an uncorrectable memory error can be repaired without a reboot operation. While initially booting a hypervisor, a special software Application Programming Interface (API) can be loaded between a BIOS System Management Mode (SMM) code and the hypervisor. Once the host server computer is booted and a number of virtual machines are executing, a memory error (e.g., uncorrectable error correction code (UECC)) can occur. In response, the hypervisor calls into the special software API identifying the defective memory rows that the BIOS needs to repair. The BIOS starts a soft Post Package Repair (PPR) process on those rows and gives back control to the hypervisor. When the repair is completed, the hypervisor loads a scrubbing virtual machine and validates that the memory is corrected. After the repair is validated, the hypervisor allows the available partition to take a new customer instance.

Abstract: A system performs a registration process for monitoring a respective address range, by: receiving, from an application, a first command to monitor a first address range in a kernel; registering, in the kernel, the first address range; creating a monitoring state window in the kernel, the monitoring state window indicating that the first address range is valid; and providing, to the application, read-only access to the monitoring state window. The system detects, in the kernel based on a previous state of a mapping of virtual addresses to physical addresses, a change associated with a memory mapping of a second address range. The system updates the monitoring state window by invalidating address ranges overlapping with the second address range. Responsive to the first address range being valid, the system bypasses the registration process for the first address range.

Abstract: A memory device and a method for protecting the same are provided. The memory device includes a controller configured to refresh one of a plurality of word lines during a first refresh cycle in response to a refresh signal, a random number generator configured to generate a first number, a counter configured to receive the first number as an initial value of the counter, wherein the counter is configured to be turned on in response to the refresh signal, and an address register configured to store an address of a first word line active when the counter decrements to zero. The controller is configured to obtain the address of the first word line and protect a second word line during a second refresh cycle, wherein an address of the second word line is adjacent to the address of the first word line.

Abstract: Contents of the next commands are considered as part of an arbitration between virtual functions (VFs). The device controller will hold the head of the submission queues (SQ) internally. The controller is able to do so by implementing a small first in first out (FIFO) per submission queue. The second arbiter and the main arbiter, which is responsible for the command scheduling, fetches the commands from the internal small FIFO. Using this technique, the second arbiter gains visibility of the next commands that participate in the arbitration since the next commands are held internally and not in host memory.

Abstract: Data may be purged from a memory device in a manner confined to a particular partition of a memory device having two or more partitions. Logical memory blocks may be de-mapped from physical memory blocks of a first storage partition of the memory device. De-mapped physical memory blocks of the first storage partition may be listed in a local de-mapped block list uniquely associated with the first storage partition. A local purge command may be received from a host device. In response to the local purge command, at least a portion of the de-mapped physical memory blocks listed only in the local de-mapped block list are purged.

Abstract: Devices and techniques are disclosed herein for providing L2P information to a host device from a storage system, the L2P information comprising a response information unit having a limited size with separate categories of information including changed L2P region and associated subregion information, to-be-loaded L2P region and associated subregion information, and invalid L2P region and associated subregion information, wherein the information in the separate categories is based on the determined changes in the different L2P regions and the subregion information in each of the separate categories identifies specific locations of changed subregions with respect to one or more corresponding regions identified in the region information of a respective category of the response information unit.

Abstract: A computing system includes a host, a memory, and a storage device. The memory includes a volatile memory and a memory controller. The storage device is connected with the host through a first interface and includes a nonvolatile memory and a storage controller, the storage device communicating with the host through a first port, communicating with the memory through a second port, and managing the memory. The memory is connected with the storage device through a second interface that is physically separated from the first interface. In an initialization operation, the storage controller sends map data that is stored in the nonvolatile memory to the memory through the second interface. In the initialization operation, the memory controller stores the map data in the volatile memory.

Abstract: The disclosure provides methods and systems for transparent data movement between a private cloud storage ecosystem and another storage system. The other storage system may be local storage or external storage separate and apart from the private cloud storage ecosystem. Originally, metadata and the data contents of a file are both stored on local storage in the private cloud storage ecosystem. The method separates the metadata from the data contents of a file such that the metadata and data contents are independently operable. After separation and based on policy, the data content is transparently moved between the private cloud storage system and the other storage system. The data is managed and tracked such that a user, e.g., a client or external program/entity, may access the data content using the original metadata stored on the private cloud storage ecosystem, despite the movement of the data contents to the other storage system.

Abstract: Techniques are provided for design verification of a bit spreading memory. A methodology implementing the techniques according to an embodiment includes using a bit spreading geometry file to convert a logical address of the memory to a physical address. The geometry file defines a scheme by which bits of a data word stored at the logical address are spread over multiple RAMs. The method also includes writing data bits of a test data word to the physical address, causing a design simulator to simulate a read from the logical address, and comparing the result to the test data word for verification. The method further includes causing the design simulator to simulate a write of the test data word to the logical address, reading data bits from the physical address, arranging the bits into a retrieved data word, and comparing the test data word to the retrieved data word for verification.

Abstract: A method to store data in tiered storage includes receiving for data stores to be stored on the tiered storage. The tiered storage may include multiple storage tiers, each storage tier having a different performance level. Each policy defines a default storage tier for the corresponding data store that has the policy. The method includes storing the data stores on the tiered storage as blocks. Each of the blocks is stored to a corresponding one of the storage tiers based at least on the policy of the data store to which the block belongs.

Abstract: A neural processing device and transaction tracking method thereof are provided. The neural processing device comprises a first set of a plurality of neural cores, a shared memory shared by the first set of the plurality of neural cores, and a programmable hardware transactional memory (PHTM) configured to receive a memory access request directed to the shared memory from the first set of the plurality of neural cores and configured to commit or buffer the memory access request.

Abstract: A data storage device includes a memory device and a memory controller. When a sub-region of the memory device is selected based on a predetermined rule to perform a data rearrangement procedure, the memory controller determines whether the selected sub-region is a system data sub-region. When determining that the selected sub-region is not a system data sub-region, the memory controller performs the data rearrangement procedure on the selected sub-region to move data corresponding to logical addresses belonging to the selected sub-region to a memory space of the memory device having continuous physical addresses, and when determining that the selected sub-region is a system data sub-region, the memory controller does not perform the data rearrangement procedure on the selected sub-region.

Abstract: According to one embodiment of the present invention, a computer-implemented method for dynamically altering a frequency at which data scrubbing is performed on a memory device is disclosed. The computer-implemented method includes monitoring at least one of a temperature and a magnetic field of the memory device. The computer-implemented method further includes, responsive to determining that at least one of the temperature and the magnetic field of the memory device reaches and/or exceeds a predetermined threshold, respectively, increasing the frequency at which data scrubbing is performed on the memory device.

Abstract: Techniques are provided for managing a dynamic reserve capacity of a block storage system. A storage control system partitions a storage capacity of at least one storage device into a plurality of blocks for storing data. A data access operation is performed by the storage control system which results in invalidating at least a portion of data stored in a given block. In response to the invalidating, the storage control system determines a degree of invalid data in the given block, and compares the determined degree of invalid data to a utilization threshold. The storage control system designates the given block as fully utilized in response to determining that the degree of invalid data does not exceed the utilization threshold, and designates a capacity of the given block that is occupied by the invalid data to be part of a reserve capacity of the at least one storage device.

Abstract: A control method of a memory device includes: controlling a flash memory controller to transmit a command to a flash memory module; determining whether the flash memory controller is in an idle state; in response to the flash memory controller being in the idle state, determining whether an idle time of the idle state exceeds a threshold value, wherein the threshold value is less than a time required for the flash memory module to complete executing a write command or an erase command; and in response to the idle time exceeding the threshold value, controlling the flash memory controller to enter a power saving mode to turn off a part of components in the flash memory controller.