Abstract: A method to determine an extreme value of a plurality of data candidates includes storing each data candidate of a plurality of data candidates in a separate column of an associative memory, initializing a row of marker bits by setting each marker bit to a value of 1, computing a subsequent row of marker bits by performing in parallel a Boolean AND operation between a previous row of marker bits and a row of bits of the data candidates, starting with the row of most significant bits of the data candidates, performing a Boolean OR operation between the marker bits in the subsequent row of marker bits to generate a subsequent RSP value, identifying the extreme value from among the plurality of data candidates when there is only one marker bit having a value of 1 in the subsequent row of marker bits coinciding with when said subsequent RSP value is a 1, and if the identifying is false, repeating the computing on a row of next most significant bits, performing and identifying until the identifying is true.

Abstract: There are provided a memory system and an operating method thereof. The memory system includes: a memory device for storing data in a program operation, and reading stored data and temporarily store the read data in a read operation; and a controller for transmitting data to the memory device, wherein the controller includes: a flash direct memory access (DMA) for reading and outputting the data temporarily stored in the memory device in the read operation; a buffer memory for storing the data output from the flash DMA; and a host DMA for reading the data stored in the buffer memory and outputting the read data to a host, wherein a first operation of storing the data temporarily stored in the memory device in the buffer memory and a second operation of outputting the data stored in the buffer memory to the host are performed in parallel.

Abstract: A system and technique are provided for providing a service address space. The system includes a service co-processor provided with a service address space. The service co-processor is attached to a main processor where the main processor is provided with a main address space. The service co-processor creates and maintains an independent copy of the main address space in the form of the service address space. The service co-processor receives from the main processor a command packet, determines a clock value for initiating a service function designated by the command packet, and updates the service address space until reaching the clock value. The service co-processor then performs the service function at the clock value.

Abstract: Technologies disclosed herein provide cryptographic computing. An example processor includes a core to execute an instruction, where the core includes a register to store a pointer to a memory location and a tag associated with the pointer. The tag indicates whether the pointer is at least partially immutable. The core also includes circuitry to access the pointer and the tag associated with the pointer, determine whether the tag indicates that the pointer is at least partially immutable. The circuitry is further, based on a determination that the tag indicates the pointer is at least partially immutable, to obtain a memory address of the memory location based on the pointer, use the memory address to access encrypted data at the memory location, and decrypt the encrypted data based on a key and a tweak, where the tweak including one or more bits based, at least in part, on the pointer.

Abstract: A number of data access operations is tracked where the data access operations are associated with each of a plurality of portions of a translation map. The translation map maps a plurality of logical block addresses to a plurality of physical block addresses of the memory device. A criterion to perform a garbage collection operation is determined to be satisfied. The garbage collection operation is to be performed on a block of the memory component. The block for performing the garbage collection operation is identified based on the number of data access operations associated with each of the plurality of portions of the translation map. The garbage collection operation is performed on the identified block.

Abstract: Techniques for efficient continuation stack storage are disclosed. In some embodiments, when a continuation yields, the continuation stack, or portion thereof, is copied from a thread stack to a data object, referred to herein as a chunk, allocated from memory. The copied stack portion may maintain the same representation in the chunk as on the thread stack to minimize processing overhead of the operation. When the continuation resumes, the continuation stack, or some portion thereof, is copied from the chunk to the thread stack. During execution, the continuation stack that was copied may be modified on the thread stack. When the continuation yields again, the runtime environment may determine, based at least in part on whether the first object in memory is subject to a garbage collection barrier, whether to copy the modified portion of the continuation stack to the existing chunk or to allocate a new chunk.

Abstract: Generally discussed herein are systems, devices, and methods for prefetcher in a multi-tiered memory (DSM) system. A node can include a network interface controller (NIC) comprising system address decoder (SAD) circuitry configured to determine a node identification of a node to which a memory request from a processor is homed, and prefetcher circuitry communicatively coupled to the SAD circuitry, the prefetcher circuitry to determine, based on an address in the memory request, one or more addresses from which to prefetch data, the one or more addresses corresponding to respective entries in a memory of a node on a different network than the NIC.

Abstract: A memory device management system includes a first key acquisition unit that acquires a first key, a second key generation unit that generates a second key in accordance with a configuration of a memory device that is a management target, an equality determination unit that determines an equality between a value of the first key and a value of the second key, and a data erasure processing unit that erases data stored in the memory device in a case of a determination that the value of the first key and the value of the second key are different.

Abstract: Systems and methods are described for enabling garbage collection on data storage systems. Traditional garbage collection often attempts to track use of data items on an individual level, deleting each item when it is no longer used. In distributed systems, tracking use on an individual level is difficult, and may require centralized knowledge across the system with respect to individual data items. Provided herein is a “coarse-grained” garbage collection mechanism, which divides objects into logical groups referred to as “roots.” Each root has a life cycle. While active, new data can be stored in a root. While inactive, use of data within a root can cause that date to be copied to a different, active root. When the system detects that data hasn't been used in an inactive root for a threshold period, the root can be considered “dead” and data within the root may be deleted.

Abstract: Methods, systems, techniques, and devices for smart factory reset procedures are described. In accordance with examples as disclosed herein, a memory system may receive one or more commands associated with a reset procedure. The memory system may identify, in response to the one or more commands, a first portion of one or more memory arrays of the memory system as storing user data and a second portion of the one or more memory arrays as storing data associated with an operating system. The memory system may update a mapping of the memory system based on identifying the first portion and the second portion. The memory system may transfer the data associated with the operating system to a third portion of the one or more memory arrays and perform an erase operation on a subset of physical addresses of the set of physical addresses.

Abstract: Provided herein may be a memory controller configured to control a memory device. The memory controller may include a map buffer, a descriptor queue, and a descriptor controller. The map buffer may sequentially store map segments of a plurality of map segments stored in the memory device. The descriptor queue may store descriptors corresponding to the respective map segments, based on a plurality of addresses of the map buffer. The descriptor controller may search for a target descriptor among the stored descriptors based on a logical address received from a host, and reorder the stored descriptors while searching for the target descriptor.

Abstract: A method and system are provided for configurable computation and data processing. A logical processor includes an array of logic elements. The processor may be a combinatorial circuit that can be applied to modify computational aspects of an array of reconfigurable circuits. A memory stores a plurality of instructions, each instruction including an instruction-fetch data portion and an output data transfer data portion. One or more memory controllers are coupled to the memory and receive instructions and/or output data from the memory. A back buffer is coupled with the memory controller and receives instructions from the memory controller. The back buffer sequentially asserts each received instruction upon one or more memory controllers. The memory controllers transfer data received from the memory to a target, such as an array of reconfigurable logic circuits that are optionally coupled to the memory, the back buffer, and one or more additional memory controllers.

Abstract: A key-value storage architecture with data compression is shown. During the garbage collection, the controller compresses valid pieces of key-value data to generate a piece of compressed data. Each piece of key-value data is in key-value format. The controller codes the piece of compressed data to generate a first piece of compressed key-value data that is also in key-value format, and programs the first piece of compressed key-value data into the non-volatile memory.

Abstract: A method and system for intelligently provisioning resources in storage systems. Specifically, the method and system disclosed herein entail throttling the allocation of resources aiding in the performance of background service tasks on a backup storage system. That is, throughout a predicted span of a background service task, resources may be dynamically allocated towards the performance of the background service task at discrete time intervals within the predicted span, thereby improving overall system utilization.

Abstract: A storage system and an operating method thereof are disclosed. The storage system includes a nonvolatile memory that stores data; a computing device to perform data processing on input data provided from the nonvolatile memory or a host outside the storage system; and a controller to control a writing operation and a reading operation of the nonvolatile memory, monitor an operating state of the computing device while the computing device is performing the data processing, and dynamically manage power of the computing device according to a monitoring result.

Abstract: A system includes a solid-state storage array having a plurality of solid-state storage devices and a storage controller coupled to the solid-state storage array, the storage controller including a processing device, the processing device to determine that a first allocation unit has a first portion occupying a first plurality of erase blocks and a second portion sharing a second erase block with a portion of a second allocation unit. The processing device is further to relocate data of the portion of the second allocation unit sharing the second erase block with the second portion of the first allocation unit to another erase block and in response to relocating the data of the portion of the second allocation unit, reclaim the first plurality of erase blocks and the second erase block.

Abstract: Provided herein may be a storage device, a method of operating the storage device, a computing system including the storage device and a host device for controlling the storage device, and a method of operating the computing system. A memory controller may include a host interface configured to receive bad block information on one or more bad blocks of a second memory device from a host device; and a bad block processor configured to store data of one or more source bad blocks of the first memory device in one or more available memory blocks of the first memory device by controlling the first memory device, the source bad blocks of the first memory device corresponding to the bad block information, the available memory blocks being different from the source bad blocks.

Abstract: In the context of data storage, an approach to pre-fetching data prior to a read request involves receiving a read request and a next read request, and updating metadata corresponding to the read request with a next data storage address corresponding to the next read request. Responsive to again receiving the read request at a later time, the next data storage address can be read from the read request metadata and the next data can be pre-fetched from the next data storage address in advance of processing a following read request. Furthermore, the next data can be pre-fetched during read queue idle time and stored in a cache buffer, in anticipation of another incoming next read request, responsive to which the next data can be returned to the host from the buffer rather than from a read of non-volatile memory.

Abstract: Embodiments of the disclosed technology relate to a memory system, and a memory controller and a method of operating the same. In performing a recovery operation after occurrence of sudden power off (SPO), by determining whether to delete, from a memory device, journaling information associated with data stored in a target open memory block based on the state of the memory device, thereby preventing unnecessary data movement in a situation where the number of free memory blocks included in the memory device is insufficient, and maintaining the number of free memory blocks included in the memory device to a predetermined value or more.

Abstract: A scheduling system for a memory controller is provided. The system includes a scheduler configurable to receive a plurality of operation requests from a plurality of masters. The scheduler is configurable to form a sequence of one or more phases from each of the operation requests. The scheduler is configurable to arbitrate the plurality of operation requests and the one or more phases through one or more configurable policies. The system includes a sequencer configurable to receive the one or more phases and communicate with at least two flash memory devices having differing types of flash memory device interfaces through a plurality of channels.