Abstract: The disclosure is related to file-aware caching for data storage devices. In one example, a device may comprise a data storage medium, an interface circuit to communicate with a host, and a driver configured to retrieve file system information related to a structured input/output (I/O) command from the host, and select caching attributes based on the file system information. Further, a system may include a host and at least one driver operating on the host; the driver configured to intercept a I/O request initiated at the host, obtain operating system information from the host about the I/O request, and store the operating system information that it is accessible to a data storage device to allow the data storage device to implement caching attributes based on the operating system information.

Abstract: Approaches for performing memory management by a hypervisor. A host operating system and a hypervisor are executed on a device. The host operating system is not configured to access physical memory addressed above four gigabytes. The hypervisor manages memory for a device, including memory addressed above four gigabytes. When the hypervisor instantiates a virtual machine, the hypervisor may allocate memory pages for the newly instantiated virtual machine by preferentially using any unassigned memory addressed above four gigabytes before using memory allocated from the host (and hence addressed below four gigabytes).

Abstract: A technique for adapting over-provisioning space in a storage system includes determining one or more workload characteristics in the storage system. Over-provisioning space in the storage system is then adjusted to achieve a target write amplification for the storage system, based on the workload characteristics.

Abstract: A memory system has a non-volatile memory, a storage accessible at higher speed than the non-volatile memory, to store access information to the non-volatile memory before accessing the non-volatile memory, and a memory controller to control a write pulse width to the non-volatile memory based on a free space of the storage or based on the access information stored in the storage.

Abstract: A memory control circuitry has a write destination selector to select either a volatile memory or a non-volatile memory in a first storage as a write destination, for an address area in the first storage written by a processor, a write controller to write data in the write destination selected by the write destination selector, and an access information register to register information selecting the volatile memory or the non-volatile memory as the write destination, and number-of-times information indicating how many times a page of successive addresses for the address area is switched, as both information being associated with each other. When there is a write request from the processor, the write destination selector selects the write destination based on the information registered in the access information register.

Abstract: Systems and methods for managing content in a flash memory. A locking data structure is used to control access to data structures and the locking data structure is implemented in flash memory. The locking data structure is updated by overwriting the data such that the associated data structure is identified as locked or unlocked.

Abstract: Dynamic memory expansion based on data compression is described. Data represented in at least one page to be written to a main memory of a computing device is received. The data is compressed in the at least one page to generate at least one compressed physical page and a metadata entry corresponding to each page of the at least one compressed physical page. The metadata entry is cached in a metadata cache including metadata entries and pointers to the uncompressed region of the at least one compressed physical page.

Abstract: A memory system has a first memory to store first-granularity data having a granularity smaller than second-granularity data, the first memory having a memory capacity smaller than a memory capacity of a second memory storing the second-granularity data, a controller to read third-granularity data having a granularity equal to or greater than the first-granularity from the data stored in the second memory, and a data extractor to extract the first-granularity data from the third-granularity data read by the controller and to store the extracted data in the first memory.

Abstract: Techniques for archiving data over a local area network, including methods, systems, that apparatus that include machine-readable media for storing executable instructions. In some implementations, an apparatus includes a touch screen, one or more processors, a battery, non-volatile data storage device, and machine-readable media including executable instructions for performing data archiving operations. Communication with a network device connected to a local area network is established. Configuration data is obtained from the network device. The configuration data identifies one or more source devices connected to the network device over a local area network, and characteristics of the one or more source devices. A set of backup parameters are determined. An instruction is generated. The instruction specifies one or more archiving operations that, when received by the network device, cause the network device to extract data from the one or more source devices over the local area network.

Abstract: A shingled magnetic recording (SMR) hard disk drive (HDD) receives a read command for data associated with a range of logical block addresses (LBAs). In situations where a first portion of valid data associated with the range of LBAs is stored in an SMR region of the HDD and a second portion of valid data associated with the range of LBAs is stored in a non-SMR region of the HDD, the first portion is read from the SMR region in a single disk access and copied to a first buffer of the HDD, and the second portion is read from the non-SMR region in one or more disk accesses and copied to a second buffer of the HDD. The valid data associated with the range of LBAs stored in the second buffer are copied to the first buffer to be combined with valid data associated with the range of LBAs stored in the first buffer, and the combined valid data is then transferred to the host to complete execution of the read command.

Abstract: Upon receiving an erase command and a first logical address, a controller in a first mode sets, as an erasure waiting area, an erasure unit area assigned with a first physical address associated with the first logical address in a first table. The controller in the first mode replaces, in the first table, the first physical address with a physical address assigned to an erasure completion area. The controller in a second mode sets the erasure waiting area as the erasure completion area. Upon receiving a release command to release the second mode at some point in time of data erasure from the erasure waiting area, the controller changes the operation mode to a third mode. The controller operating in the third mode erases un-erased data from the erasure waiting area and changes the operation mode from the third mode to the first mode.

Abstract: A data processing method includes allocating a tag entry in a tag array for a data block; allocating a data entry in a data array for the data block when the data block is actively shared; and de-allocating the data entry when the data block is temporarily private or gets evicted in the data array.

Abstract: A system includes one or more memory devices storing instructions, and one or more processors configured to execute the instructions to perform steps of a method for providing customer data access during a migration process. The system may initiate a transfer of customer data from a source data server to a system platform and transfer a subset of the customer data to a temporary data storage. The system may modify the temporary copy of customer data and generate an instruction to modify the permanent copy of customer data. In response to the completion of the transfer of customer data from the source data server to the system mainframe, the system may then transfer and execute the instruction to modify the permanent copy of customer data.

Abstract: Systems and methods for configuring, controlling and operating a non-volatile cache are disclosed. A host system may poll a memory system as to the memory system's configuration of its non-volatile cache. Further, the host system may configure the non-volatile cache on the memory system, such as the size of the non-volatile cache and the type of programming for the non-volatile cache (e.g., whether the non-volatile cache is programmed according to SLC or the type of TRIM used to program cells in the non-volatile cache). Moreover, responsive to a command from the host to size the non-volatile cache, the memory system may over or under provision the cache. Further, the host may control operation of the non-volatile cache, such as by sending selective flush commands.

Abstract: A memory system has a first memory to be accessed per first data size, a second memory to be accessed per second data size smaller than the first data size, the second memory being accessible at a higher speed than the first memory; and a third memory to store address conversion information that converts an address for accessing the second memory into an address for accessing the first memory. The first and third memories are non-volatile memories.

Abstract: Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. In accordance with one embodiment of the present disclosure, a method for improving performance and reducing power consumption in memory may include tracking whether individual units of a memory system are active or inactive. The method may also include placing inactive individual units of the memory system in a self-refresh mode, such that the inactive individual units self-refresh their contents. The method may further include placing active individual units of the memory system in a command-based refresh mode, such that the active individual units are refreshed in response to a received command to refresh their contents.

Abstract: A cache memory system has a first cache memory, a second cache memory which comprises a nonvolatile memory capable of generating a plurality of regions having different access speeds and has access priority lower than the first cache memory, and a cache controller which carries out a control where data to be stored in the second cache memory is sorted to the plurality of regions and stored thereto in accordance with access conditions with respect to the first cache memory.

Abstract: An electronic memory arrangement having at least three memory areas, a memory control unit, and a writing memory-accessing unit configured to carry out write access. A reading memory-accessing unit is configured to carry out read accesses. The memory control unit determines read and write access to the at least three memory areas, and the memory control unit is configured such that after the writing of a first data packet to one of the three memory areas, a following second data packet to be written is written to one on the three memory area to which read access does not place simultaneously during the write access of the second data packet.

Abstract: A mass data storage system, which comprises: a controller for issuing and receiving signals to carry out memory operations; a motherboard comprising at least one first connector and providing signal pathways for establish a ring from the controller via each of the at least one first connector and back to the controller; and at least one non-volatile memory module comprising a second connector electrically connected to a chain of non-volatile memory devices, wherein mating of the second connector with a given one of the at least one first connector causes the chain of non-volatile memory devices to be inserted into the ring, thereby to allow the controller to carry out the memory operations on the non-volatile memory devices in the chain.

Abstract: A processor includes a first memory interface to be coupled to a plurality of dual in-line memory module (DIMM) sockets located off-package, a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package, and a multi-level memory controller (MLMC). The MLMC is to: control the DIMMs disposed in the plurality of DIMM sockets as main memory in a one-level memory (1LM) configuration; detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of a low-power DIMM disposed in one of the DIMM sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and control the low-power DIMM as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.