Abstract: Techniques and apparatus are provided for improved diagnostics of downhole dynamometer data for control and troubleshooting of reciprocating rod lift systems. A method for pump fillage determination for a reciprocating rod lift system is provided. The method generally includes measuring downhole data during a pump cycle, wherein the downhole data comprises a first plurality of data points associated with an upstroke of the pump cycle and a second plurality of data points associated with a downstroke of the pump cycle, each data point comprising a rod position value and an associated rod load value; converting the data points to non-dimensional data points, calculating non-dimensional slope values between non-dimensional data points; and determining pump fillage based, at least part, on the calculated non-dimensional slope values.

Abstract: The tire state detecting device includes a calculating unit that calculates an acceleration difference of the gravitational acceleration value acquired at a first acquiring angle and the gravitational acceleration value acquired at a second acquiring angle; a storage unit that stores a correction formula defined in advance based on an angular difference between the adjacent acquiring angles and an angular difference of the first acquiring angle and the second acquiring angle, and corrects the first acquiring angle to an angle determined in advance from the acceleration difference; a transmission unit that transmits a transmission signal including information indicating the angle determined in advance in addition to information indicating the state of the tire; and a control unit that causes the transmission signal to be transmitted to a wheel position specifying device.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.

Abstract: Disclosed is a method for determining an overlay error between at least two layers in a multiple layer sample. An imaging optical system is used to measure multiple measured optical signals from multiple periodic targets on the sample, and the targets each have a first structure in a first layer and a second structure in a second layer. There are predefined offsets between the first and second structures A scatterometry overlay technique is used to analyze the measured optical signals of the periodic targets and the predefined offsets of the first and second structures of the periodic targets to thereby determine an overlay error between the first and second structures of the periodic targets. The scatterometry overlay technique is a phase based technique, and the imaging optical system is configured to have an illumination and/or collection numerical aperture (NA) and/or spectral band selected so that a specific diffraction order is collected and measured for the plurality of measured optical signals.

Abstract: According to one embodiment, the silicon layer includes phosphorus. The buried layer is provided on the silicon layer. The stacked body is provided on the buried layer. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The semiconductor body extends in a stacking direction of the stacked body through the stacked body and through the buried layer, and includes a sidewall portion positioned at a side of the buried layer. The silicon film is provided between the buried layer and the sidewall portion of the semiconductor body. The silicon film includes silicon as a major component and further includes at least one of germanium or carbon.

Abstract: A method of manufacturing a semiconductor device, including implanting hydrogen atoms from a second principal surface of a semiconductor substrate, forming a plurality of second semiconductor layers that each have a carrier concentration higher than that of the first semiconductor layer and that have carrier concentration peak values at different depths from the second principal surface of the semiconductor substrate, applying a heat treatment process to promote generation of donors from the hydrogen atoms, implanting an impurity from the second principal surface of the semiconductor substrate, forming a third semiconductor layer in the semiconductor substrate at the second principal surface thereof, and applying another heat treatment process to locally heat the semiconductor substrate, so as to reduce the carrier concentration at an interface between the third semiconductor layer and the second semiconductor layer adjacent to the third semiconductor layer.

Abstract: A semiconductor device according to an embodiment includes a first diode portion including a first trench extending in a first direction, and a first trench electrode; a second diode portion adjacent to the first diode portion in the first direction and includes a second trench extending in the first direction, and a second trench electrode and of which the width in the first direction is greater than the width of the first diode portion in a second direction perpendicular to the first direction; and a first IGBT portion adjacent to the first diode portion in the second direction and is adjacent to the second diode portion in the first direction and includes a third trench extending in the first direction, and a first gate electrode.

Abstract: A method and device for determining values of a magnetic field component of a magnetic vector field. A method for determining values of a magnetic field component of a magnetic vector field, comprising: determining first distribution data comprising values of the magnetic field component, for a first predetermined area defined along a predetermined surface; determining second distribution data comprising second values of the component of the magnetic field for a second predetermined area defined along a second predetermined surface, wherein the first and the second predetermined surfaces are parallel; wherein determining second distribution data comprises manipulation of the first distribution data based on making use of intrinsic physical properties of the magnetic field; and associated device.

Abstract: An optical module includes a substrate, a lid, a light-emitting component, a first sensor and a second sensor. The lid is disposed on a surface of the substrate. The lid defines a first opening, a second opening and a third opening. The second opening is between the first opening and the third opening. The light-emitting component is disposed on the surface of the substrate and in the first opening. The first sensor is disposed on the surface of the substrate and in the second opening. The second sensor is disposed on the surface of the substrate and in the third opening.

Abstract: A semiconductor device is provided, in which a loss of a sensing element is small. A semiconductor device including a semiconductor substrate is provided, the semiconductor device including: an upper-surface electrode that is provided on an upper surface of the semiconductor substrate; a sensing electrode that is provided on the upper surface of the semiconductor substrate and is separated from the upper-surface electrode; a lower-surface electrode that is provided on a lower surface of the semiconductor substrate; a main transistor portion that is provided on the semiconductor substrate and is connected to the upper-surface electrode and the lower-surface electrode; a main diode portion that is provided on the semiconductor substrate and is connected to the upper-surface electrode and the lower-surface electrode; and a sense diode portion that is provided to the semiconductor substrate and is connected to the sensing electrode and the lower-surface electrode.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. An insulating fill material layer and drain select gate electrodes are located over the alternating stack. A group of memory stack structures extends through the alternating stack, and is arranged as rows of memory stack structures. Each memory stack structure is entirely encircled laterally by a respective one of the drain select gate electrodes. The insulating fill material layer includes a drain select level isolation structure extending between neighboring rows of memory stack structures and including a pair of sidewalls containing a respective laterally alternating sequence of planar vertical sidewall portions and concave vertical sidewall portions, and a drain select level field portion adjoined to the drain select level isolation portion.

Abstract: A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer.

Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.

Abstract: A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.

Abstract: In certain embodiments, a control/optimization system includes an instantiated model object stored in memory on a model server. The model object includes a model of a plant or process being controlled. The model object comprises an interface that precludes the transmission of proprietary information via the interface. The control/optimization system also includes a decision engine software module stored in memory on a decision support server. The decision engine software module is configured to request information from the model object through a communication network via a communication protocol that precludes the transmission of proprietary information, and to receive the requested information from the model object through the communication network via the communication protocol.

Abstract: An embodiment package-on-package (PoP) device includes a package structure, a package substrate, and a plurality of connectors bonding the package structure to the package substrate. The package structure includes a logic chip bonded to a memory chip, a molding compound encircling the memory chip, and a plurality of conductive studs extending through the molding compound. The plurality of conductive studs is attached to contact pads on the logic chip.

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device and techniques for fabricating a semiconductor device. In certain aspects, the semiconductor device includes a fin, a first non-insulative region disposed adjacent to a first side of the fin, and a second non-insulative region disposed adjacent to a second side of the fin. In certain aspects, the first non-insulative region and the second non-insulative region are separated by a trench, at least a portion of the trench being filled with a dielectric material disposed around the fin.

Abstract: A method for fabricating a non-volatile, ferroelectric random access memory (F-RAM) device with a reduced number of masking and etching steps is described. In one embodiment, the method includes forming an opening in an insulating layer over a surface of a substrate to expose a portion of the surface, and forming first spacers on sidewalls of the opening. A conductive layer is formed on the portion of the surface exposed in the opening and separated from the first spacers on the sidewalls of the opening by a gap therebetween. A bottom electrode of a ferroelectric capacitor is formed over the conductive layer and in the gap laterally of the conductive layer, a ferroelectric dielectric formed on the bottom electrode between the first spacers, and a top electrode formed on the ferroelectric dielectric.

Abstract: A semiconductor device has a top metal layer, a first passivation layer over the top metal layer, a first redistribution layer over the first passivation layer, a first polymer layer, and a first conductive via extending through the first polymer layer. The first polymer layer is in physical contact with the first passivation layer.

Abstract: The present disclosure includes a method including determining a spatial region for analysis and selecting a segment of time for analysis, analyzing and correcting a plurality of traces from a plurality of receivers using an iterative non-linear inversion algorithm, wherein each iteration of the non-linear algorithm corrects the plurality of traces using at least one set of parameters defining a microseismic event, determining whether a final stack value of the plurality of traces corrected based on the at least one set of parameters of a final iteration of the iterative non-linear inversion algorithm exceeds a predetermined threshold and upon a determination that the final stack value exceeds the predetermined threshold, detecting a microseismic event defined by the at least one set of parameters of final iteration. The present disclosure also includes associated systems and computer-readable media.