Patents Examined by Jarrett Stark
  • Patent number: 10199394
    Abstract: Provided is a display device with high display quality. The display device includes a transistor over a substrate, an inorganic insulating film over the transistor, an organic insulating film over the inorganic insulating film, a capacitor electrically connected to the transistor, and a pixel electrode over the organic insulating film. The transistor includes a gate electrode over the substrate, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film in contact with one surface of the oxide semiconductor film, and a pair of conductive films in contact with the oxide semiconductor film. The capacitor includes a metal oxide film over the gate insulating film, the inorganic insulating film, and a first light-transmitting conductive film over the inorganic insulating film. The pixel electrode is formed of a second light-transmitting conductive film and in contact with one of the pair of conductive films and the first light-transmitting conductive film.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: February 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroyuki Miyake, Masahiro Katayama
  • Patent number: 10190248
    Abstract: A system for the remote monitoring of washing machines cleanliness to a pre-certified cleanliness standard includes washing machines having wash processors to wash items according to pre-determined pre-certified recipes using pre-certified consumables. The wash processors are adapted to communicate over the internet with a remotely located administrator processor, to exchange information on a repeating, short-time interval. The wash processors provide to the administrator processor the volumetric consumption of consumables over successive wash loads. In each of said at least one washing machine according to said recipes, wherein said recipes correspond to characteristics of the wash items in each corresponding wash load and the corresponding nature of the spoilage. The recipes and the consumables have been independently pre-certified for use in the washing machines so as to clean and restore the wash items to a pre-determined certification standard of cleanliness.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: January 29, 2019
    Inventor: Randall J. Rhode
  • Patent number: 10164087
    Abstract: To provide a semiconductor device equipped with a snubber portion having an improved withstand voltage and capable of reducing a surge voltage at turn-off of an insulated gate field effect transistor portion. The concentration of a first conductivity type impurity in a snubber semiconductor region is greater than that in a drift layer. The thickness of a snubber insulating film between the snubber semiconductor region and a snubber electrode is greater than that of a gate insulating film between a gate electrode and a body region.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: December 25, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Senichirou Nagase, Tsuyoshi Kachi, Yoshinori Hoshino
  • Patent number: 10147787
    Abstract: A semiconductor structure includes a semiconductor substrate, at least one source drain structure, an insulating layer, and a gate. The semiconductor substrate includes a base portion and at least one fin. The fin is disposed on the base portion. The source drain structure is disposed on at least one sidewall of the fin. The insulating layer is disposed between the base portion and the source drain structure to isolate the base portion and the source drain structure. The gate is disposed on the fin.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: December 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Tai-Yuan Wang
  • Patent number: 10134898
    Abstract: Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: November 20, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jocelyne Gimbert
  • Patent number: 10134865
    Abstract: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Wei Yang, Chi-Wen Liu, Hao-Hsiung Lin, Ling-Yen Yeh
  • Patent number: 10134675
    Abstract: An advanced metal conductor structure is described. An integrated circuit device including a substrate having a patterned dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed over the set of features in the patterned dielectric. A metal layer fills a first portion of the set of features and is disposed over the adhesion promoting layer. A ruthenium layer is disposed over the metal layer. A cobalt layer is disposed over the ruthenium layer fills a second portion of the set of features. The cobalt layer is formed using a physical vapor deposition process.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 10134881
    Abstract: A heterojunction bipolar transistor (HBT) thermal sensing device includes a well structure as a layer between an HBT sub-collector and an HBT substrate. In one instance, the HBT sub-collector contacts an emitter, a collector, and a base of the HBT thermal sensing device. The HBT thermal sensing device also includes a first side electrode in electrical contact with the quantum well structure and a second side electrode in electrical contact with the quantum well structure.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: November 20, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Gengming Tao, Xia Li, Bin Yang
  • Patent number: 10128379
    Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Min Song, Woo Seok Park, Geum Jong Bae, Dong Il Bae, Jung Gil Yang
  • Patent number: 10121857
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: November 6, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
  • Patent number: 10121795
    Abstract: A method for producing a pillar-shaped semiconductor memory device includes forming a mask on a semiconductor substrate and etching to form a semiconductor pillar on the semiconductor substrate. A tunnel insulating layer is formed and a data charge storage insulating layer is formed so as to surround the tunnel insulating layer, and a first conductor layer and a second interlayer insulating layer are formed on the semiconductor pillar. S stacked material layer is formed in a direction perpendicular to an upper surface of the semiconductor substrate, the stacked material layer including the first conductor layer and the second interlayer insulating layer. Data writing and erasing due to charge transfer between the semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer is performed by application of a voltage to the first conductor layer.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: November 6, 2018
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 10115627
    Abstract: According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: October 30, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yumiko Miyano
  • Patent number: 10115808
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: October 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Tien-Shun Chang, Wei-Ting Chien, Chih-Pin Tsao, Hou-Ju Li
  • Patent number: 10109589
    Abstract: An integrated fan-out package including a die attach film, an integrated circuit component, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component is disposed on the die attach film and includes a plurality of conductive terminals. The die attach film includes an uplifted edge which raises toward sidewalls of the integrated circuit component. The insulating encapsulation encapsulates the uplifted edge and the integrated circuit component. The redistribution circuit structure is disposed on the integrated circuit component and the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals of the integrated circuit component. A method of fabricating the integrated fan-out package are also provided.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 10104775
    Abstract: A semiconductor device according to the present invention includes a ceramic substrate, a plurality of circuit patterns arranged on a surface of the ceramic substrate, a semiconductor element arranged on an upper surface of at least one circuit pattern, and a sealing resin for sealing the ceramic substrate, the plurality of circuit patterns, and the semiconductor element, in which an undercut part is formed in opposed side surfaces of the circuit patterns adjacent to one another, the undercut part is configured such that an end of an upper surface of the circuit pattern protrudes outside the circuit pattern more than an end of a lower surface of the circuit pattern on the ceramic substrate, and the undercut part is also filled with the sealing resin.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: October 16, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoki Yoshimatsu, Masayoshi Shinkai, Taketoshi Shikano, Daisuke Murata, Nobuyoshi Kimoto, Yuji Imoto, Mikio Ishihara
  • Patent number: 10090266
    Abstract: A semiconductor device includes a semiconductor chip having a semiconductor substrate with chip and boundary regions, and an integrated circuit on the chip region. A center pad is provided on the chip region and on the integrated circuit, and a boundary pad is provided on the boundary region. The semiconductor device further includes a first lower insulating structure having a contact hole exposing the center pad, a second lower insulating structure, at the same vertical level as the first lower insulating structure, and having a first opening exposing the boundary pad to an outside of the first lower insulating structure, a conductive pattern including a contact portion, a conductive line portion, and a bonding pad portion, and an upper insulating structure formed on the first lower insulating structure and the conductive pattern and having a second opening exposing the bonding pad portion to the outside of the semiconductor chip.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: October 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ae-Hee Choi, Sang-ki Kim, Ahyun Jo, Kyo-Seon Choi
  • Patent number: 10083968
    Abstract: A semiconductor structure for a memory device includes a substrate including a memory cell region and a peripheral circuit region defined thereon, at least an active region formed in the peripheral circuit region, a buried gate structure formed in the active region in the peripheral circuit region, a conductive line structure formed on the buried gate structure, and at least a bit line contact plug formed in the memory cell region.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: September 25, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Yukihiro Nagai
  • Patent number: 10079362
    Abstract: An organic light-emitting display device includes a substrate, a display unit on the substrate, and a thin film encapsulation unit configured to encapsulate the display unit, and including a corrugated portion including a first layer and a second layer that are sequentially stacked, wherein the first layer includes a material having a lower modulus of elasticity than the second layer, and wherein a corrugated surface is formed at an upper surface of the first layer and a lower surface of the second layer due to a difference in the moduli of elasticity of the first layer and the second layer.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: September 18, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jongwoo Kim, Heungkyoon Lim, Yongtack Kim, Jiyoung Moon, Minho Oh, Deokchan Yoon, Seungjae Lee, Yoonhyeung Cho, Jaeheung Ha
  • Patent number: 10079292
    Abstract: A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10074631
    Abstract: Packages and packaging methods for semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a molding compound and a plurality of through-vias disposed in the molding compound. The package includes an interconnect structure disposed over the plurality of through-vias and the molding compound. The interconnect structure includes a metallization layer. The metallization layer includes a plurality of contact pads and a fuse.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Hsien-Wei Chen, Der-Chyang Yeh, An-Jhih Su