Patents Examined by Jasmine Clark
  • Patent number: 10269673
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound. The molding compound is thicker than the integrated circuit die.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Chih-Wei Lin, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 10246775
    Abstract: An apparatus for forming a thin film on a substrate in a processing container under vacuum atmosphere by alternately supplying a first gas and a second gas, which are process gases, onto the substrate, including: n first processing regions spaced from each other along circumferential direction of the processing container and used to process the substrate by supplying the first gas; n second processing regions formed between the n first processing regions along the circumferential direction and used to process the substrate by supplying the second gas; an isolation part isolating the n first processing regions and the n second processing regions; mounting parts disposed to be revolved along the circumferential direction and used to mount substrates; and a control part intermittently revolving mounting parts so that the substrates are alternately located in the n first processing regions and the n second processing regions while a revolution is stopped.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: April 2, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hitoshi Kato
  • Patent number: 10249601
    Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip with connection pads on its active surface disposed in the through-hole and a first encapsulant encapsulating at least portions of the first connection member and the semiconductor chip. A second connection member is disposed below the first connection member and the semiconductor chip. A first heat dissipation member is formed in the first connection member. A component package is disposed on the fan-out semiconductor package and includes a wiring substrate connected to the first connection member through connection terminals, electronic components disposed on the wiring substrate, a second encapsulant encapsulating at least portions of the electronic components, and a second heat dissipation member formed in the wiring substrate. At least one of the electronic components is connected to the first heat dissipation member through the second heat dissipation member.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: April 2, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Won Gi Kim
  • Patent number: 10249516
    Abstract: Arrays of objects on a substrate having void-free underfill as well as methods and systems of forming the same include forming a void-free layer of underfill material between a substrate and an array of multiple objects positioned on the substrate. The void-free layer of underfill material is cured to form a protective cured underfill layer that provides structural support to connections between the objects and the substrate.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Evan George Colgan, Michael Anthony Gaynes, Katsuyuki Sakuma, Donald Alan Merte
  • Patent number: 10249823
    Abstract: A fullerene derivative may be included in photoelectric devices and image sensor. Optical absorption characteristics of a thin film including the fullerene derivative may be shifted toward a short wavelength compared with those of the thin film including the unsubstituted C60 fullerene, for example, a thin film including the fullerene derivative may be associated with a peak absorption wavelength (?max) that is be shorter than that of a thin film including the unsubstituted C60 fullerene.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: April 2, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hiromasa Shibuya, Tadao Yagi, Rie Sakurai, Yeong Suk Choi, Yutaka Matsuo
  • Patent number: 10242938
    Abstract: The disclosure is directed to a circuit on a substrate, such as a leadframe package, that includes shunt to measure current. The shunt is an arched conductor positioned to bridge over a die mounted on the package with voltage measurement terminals of the die electrically connected to the shunt. The techniques of this disclosure determine the shunt material, shunt size and shape to accurately control the value of the resistance of the shunt. The arrangement of the die and the shunt may include advantages of maintaining a small package size and allow accurate temperature compensation. The shunt may be long enough to have a measurable resistance that may be used to determine the current through the shunt. In some examples, the arrangement of the die and the shunt may provide additional structural support to the circuit.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: March 26, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Wolfgang Furtner
  • Patent number: 10244628
    Abstract: Printed electronic device comprising a substrate onto at least one surface of which has been applied a layer of an electrically conductive ink comprising functionalized graphene sheets and at least one binder. A method of preparing printed electronic devices is further disclosed.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: March 26, 2019
    Assignees: THE TRUSTEES OF PRINCETON UNIVERSITY, VORBECK MATERIALS CORPORATION
    Inventors: John M. Crain, John S. Lettow, Ilhan A. Aksay, Sibel Korkut, Katherine S. Chiang, Chuan-Hua Chen, Robert K. Prud'homme
  • Patent number: 10231338
    Abstract: Methods of forming a package structures comprising a trench are described. An embodiment includes a first die disposed on a first substrate, and at least one interconnect structure disposed on a peripheral region of the first substrate. A molding compound is disposed on a portion of the first substrate and on the first die, wherein a trench opening is disposed in the molding compound that is located between the at least one interconnect structure and the first die.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: March 12, 2019
    Assignee: INTEL CORPORATION
    Inventors: Naga Sivakumar Yagnamurthy, Huiyang Fei, Pramod Malatkar, Prasanna Raghavan, Robert Nickerson
  • Patent number: 10229918
    Abstract: Devices and methods of fabricating integrated circuit devices using semi-bidirectional patterning are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a dielectric layer, a first, a second, and a third hardmask layer, and a lithography stack; patterning a first set of lines; patterning a second set of lines between the first set of lines; etching to define a combination of the first and second set of lines; depositing a second lithography stack; patterning a third set of lines in a direction perpendicular to the first and second set of lines; etching to define the third set of lines, leaving an OPL; depositing a spacer over the OPL; etching the spacer, leaving a vertical set of spacers; and etching the second hardmask layer using the third hardmask layer and the set of vertical spacers as masks.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: March 12, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Atsushi Ogino
  • Patent number: 10229892
    Abstract: A semiconductor package includes at least one semiconductor element, an encapsulant, a first circuitry, a second circuitry and at least one first stud bump. The encapsulant covers at least a portion of the semiconductor element. The encapsulant has a first surface and a second surface opposite to the first surface. The first circuitry is disposed adjacent to the first surface of the encapsulant. The second circuitry is disposed adjacent to the second surface of the encapsulant. The first stud bump is disposed in the encapsulant, and electrically connects the first circuitry and the second circuitry. The first stud bump contacts the second circuitry directly.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 12, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Bernd Karl Appelt
  • Patent number: 10224332
    Abstract: A semiconductor device includes a substrate with an active region, a plurality of conductive line structures on the substrate, an insulating layer separating the plurality of conductive line structures from the substrate, a contact plug between every two adjacent conductive line structures, an insulating spacer structure between each conductive line structure and a corresponding contact plug, a landing pad connected to each contact plug, and a landing pad insulation pattern having an asymmetrical shape based on a vertical axis of the landing pad that extends along a normal to the substrate. The landing pad insulation pattern includes a first portion overlapping the conductive line structures and a second portion overlapping the contact plug, the first and second portions being on opposite sides of the vertical axis.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: March 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nam-gun Kim, Sang-min Lee, Tae-seop Choi, Kon Ha, Seung-jae Lee
  • Patent number: 10224262
    Abstract: Heat spreader lids and package assemblies including a heat spreader lid. The heat spreader lid has a central region configured to be coupled with an electronic component, a peripheral region configured to be coupled with a substrate, and a connecting region arranged between the central region and the peripheral region. The connecting region is configured to impart stress relief to the central region.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: March 5, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kathryn C. Rivera, Janak G. Patel, David Stone, Samantha Donovan
  • Patent number: 10217766
    Abstract: A radio frequency fully depleted silicon on insulator (RF-FDSOI) device and method of fabrication are provided. A silicon wafer for digital circuits is constructed using fully depleted silicon on insulator technology having a thin buried oxide layer. Localized areas of the silicon wafer are constructed for radio frequency circuits and/or passive devices. The silicon wafer has a silicon substrate having a resistivity greater than 1 K?·cm. The localized areas of the silicon wafer may include a trap rich layer implanted underneath a thin buried oxide layer. The localized areas of the silicon wafer may include a buried oxide layer that is thicker than the thin buried oxide layer. The thicker oxide layer is between 20 and 2000 nm thick. The localized areas of the silicon wafer may include a trap rich layer implanted underneath the thicker buried oxide layer.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Jean-Olivier Plouchart
  • Patent number: 10211121
    Abstract: A heat sink for a semiconductor chip device includes cavities in a lower surface thereof for receiving electrical components on a top surface of the semiconductor chip, and a pedestal extending through an opening in the semiconductor chip for contacting electrical components on a bottom surface of the semiconductor chip. A lid may also be provided on the bottom surface of the semiconductor chip for protecting the electrical components and for heat sinking the electrical components to an adjacent device or printed circuit board.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: February 19, 2019
    Assignee: Elenion Technologies, LLC
    Inventor: Nathan A. Nuttall
  • Patent number: 10204893
    Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: February 12, 2019
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Arkalgud R. Sitaram, Paul Enquist
  • Patent number: 10199223
    Abstract: An etch stop layer comprises a metal oxide comprising a metal selected from the group consisting of metals of Group 4 of the periodic table, metals of Group 5 of the periodic table, metals of Group 6 of the periodic table, and yttrium. The metal oxide forms exceptionally thin layers that are resistant to ashing and HF exposure. Subjecting the etch stop layer to both ashing and HF etch processes removes less than 0.3 nm of the thickness of the etch stop layer, and more preferably less than 0.25 nm. The etch stop layer may be thin and may have a thickness of about 0.5-2 nm. In some embodiments, the etch stop layer comprises tantalum oxide (TaO).
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: February 5, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Dieter Pierreux, Werner Knaepen, Bert Jongbloed
  • Patent number: 10192734
    Abstract: Si-containing film forming compositions comprising Si—C free and volatile silazane-containing precursors are disclosed. The compositions may be used to deposit high purity thin films. The Si—C free and volatile silazane-containing precursors have the formulae: [(SiR3)2NSiH2]m—NH2-m—C?N, with m=1 or 2;??(a) [(SiR3)2NSiH2]n—NL3-n,with n=2 or 3;??(b) (SiH3)2NSiH2—O—SiH2N(SiH3)2; and??(c) (SiR?3)2N—SiH2—N(SiR?3)2;??(d) with each R independently selected from H, a dialkylamino group, or an amidinate; each R? independently selected from H, a dialkylamino group, or an amidinate, with the provision that all R? are not H; and L is selected from H or a C1-C6 hydrocarbyl group.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: January 29, 2019
    Assignees: L'Air Liquide, Société Anonyme pour l'Etude et l'Exploration des Procédés Georges Claude, Air Liquide Advanced Materials, Inc., Air Liquide Advanced Materials LLC
    Inventors: Antonio Sanchez, Gennadiy Itov, Reno Pesaresi, Jean-Marc Girard, Peng Zhang, Manish Khandelwal
  • Patent number: 10192962
    Abstract: A semiconductor device including, a semiconductor layer including a plurality of first trenches formed therein and a second trench formed in a region between the first trenches, channel regions formed in regions between the first and second trenches in a surface layer portion of the semiconductor layer, field plate electrodes embedded at bottom portion sides of the respective first trenches, first gate electrodes embedded at opening portion sides of the respective first trenches so as to face the channel regions across first gate insulating films above the field plate electrodes, second insulating films interposed between the field plate electrodes and the first gate electrodes, an embedded insulating film embedded to an intermediate portion of the second trench, and a second gate electrode embedded in the second trench so as to face the channel regions across a second gate insulating film above the embedded insulating film.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: January 29, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Yuto Osawa
  • Patent number: 10186466
    Abstract: An electronic device includes a carrier substrate with at least one integrated-circuit chip mounted on a front face of the carrier substrate. An encapsulation block on the front face and embedding the integrated-circuit chip has a periphery with corners. The encapsulating block further has, in at least one local zone located in at least one corner and from the front face of the carrier substrate, a smaller thickness than a thickness of the encapsulation block at least in a surrounding zone. The electronic device is manufactured by a process in which the zone of smaller thickness is obtained by molding or by machining.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: January 22, 2019
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Benoit Besancon, Luc Petit
  • Patent number: 10177067
    Abstract: A manufacturing method including following steps is provided. A substrate that includes a core layer, a first conductive layer, and a second conductive layer is provided. A heat conducting channel is formed in the substrate, and an adhesion layer is formed on the second conductive layer to cover a side of the heat conducting channel. A heat conducting element and a buffer layer are placed into the heat conducting channel, and a gap is formed between either the heat conducting element or the buffer layer and an inner side surface of the heat conducting channel. The gap is filled with a first insulant material, and the adhesion layer and the buffer layer are removed to form a cavity and expose the heat conducting element. The first conductive layer and the second conductive layer are patterned to form a first patterned circuit layer and a second patterned circuit layer, respectively.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: January 8, 2019
    Assignee: Subtron Technology Co., Ltd.
    Inventors: Chin-Sheng Wang, Chih-Hsien Cheng, Shih-Hao Sun