Abstract: An antenna device and a method for manufacturing the same are provided. The antenna device includes a carrier and an antenna element. The carrier includes a plurality of pads and has a surface exposing the pads. The antenna element is disposed above the pads. A lateral surface of one of the pads is farther from a central axis of the antenna element substantially perpendicular to the surface than from a lateral surface of the antenna element.

Abstract: An antenna system can include a ground plane and a driven element spaced apart from the ground plane. The antenna system can include a parasitic element disposed proximate to the driven element. The parasitic element can be coupled to the ground plane by a first coupling and a second coupling. The second coupling can be independent from the first coupling. For instance, the first coupling can include one or more tunable components. The second coupling can fix the parasitic element to the ground plane.

Abstract: Controlling the color temperature of a composite light source including at least one discrete-spectrum light source is disclosed. For example, the color temperature of a composite light source including at least one discrete-spectrum light source may be determined and/or adjusted based on one or more of the ambient color temperature of a space, the actual temperature of the space, the relative brightness of the space, the occupancy of the space, a time clock, a demand response command (e.g., from an electrical utility), the absolute location of the composite light source, the location of the composite light source relative to other light sources, inputs from a camera or other external devices, the operation of appliances or other machines in the vicinity of the composite light source, media content being utilized in the vicinity of the composite light source, and/or other sensor inputs.

Abstract: A base configured to be joined with other bases to form a substrate for an antenna array comprises a body, a plurality of male interconnecting features, and a plurality of female interconnecting features. The body includes a front surface and a rear surface and a plurality of edges positioned therebetween. The front surface or the rear surface is configured to retain an antenna. The male interconnecting features of a first base connect with the female interconnecting features of a second base when the first base is joined with the second base to form the substrate or a portion of the substrate.

Abstract: An example apparatus includes a memory device comprising a plurality of banks of memory cells. A particular bank of memory cells among the plurality of banks includes a system processor resident on a particular bank of the plurality of banks.

Abstract: A vehicle headlamp control circuit is configured to control a vehicle headlamp comprising a plurality of lighting elements. The vehicle headlamp control circuit may comprise a memory that stores information for controlling the plurality of lighting elements, and a driver circuit that drives the plurality of lighting elements based on the information, wherein the information compensates for one or more failed elements of the plurality of lighting elements.

Abstract: An antenna array module includes two or more antenna elements arranged in an array, each of the two or more antenna elements formed as a respective integrated passive device (IPD), and a multi-layer printed circuit board (PCB) including one or more metal layers forming one or more feed lines of the antenna elements. The antenna array module may include a radio frequency (RF) front end integrated circuit disposed on an opposite side of the multi-layer PCB from the two or more antenna elements. One or more signal output pins of the RF front end integrated circuit may be connected to the one or more feed lines. The antenna array module may include conductive contacts external to the multi-layer PCB for routing input signals through the multi-layer PCB to one or more signal input pins of the RF front end integrated circuit.

Abstract: The present invention is related to a condensation prevention type transmission window for a CMS module test chamber, the transmission window being provided at the module test chamber. The condensation prevention type transmission window includes: a multilayer glass panel in which heating wires are coated on upper, lower, left, and right side surfaces thereof; and an air injector provided at each of opposite surfaces of the transmission window to inject air from an upper side edge and/or a lower side edge of the transmission window and to form an air curtain. The present invention provides the condensation prevention type transmission window for a CMS module test chamber, which prevents freezing and fogging on inside and outside surfaces of the transmission window of the CMS module test chamber varying in a temperature range from 40° C. to +125° C.

Abstract: An integrated circuit includes first and second bus terminals, a pass-gate transistor, first and rising time accelerator (RTA) control circuits, and first and second falling time accelerator (FTA) control circuits. The pass-gate transistor couples between the first and second bus terminals. The first RTA control circuit couples to the first bus terminal, detects a rising edge on the first bus terminal, and accelerates the rising edge on the first bus terminal. The first FTA control circuit couples to the first bus terminal, detects a falling edge on the first bus terminal having a slope below a threshold, and accelerates the falling edge on the first bus terminal. The second RTA and FTA control circuits function similar to the first RTA and FTA control circuits but with respect to the second bus terminal.

Abstract: A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.

Abstract: A microcontroller includes an input pin and internal pull-up and pull-down circuits. External pull-up and pull-down circuits are also coupled to the input pin. The microcontroller is operable according to different configuration modes which include configuring the input pin in a floating state. A control logic then configures the internal pull-up and pull-down circuits according to an internal pull-up mode to acquire a first input voltage signal (at a first logic value) from the input pin, and further configure the internal pull-up and pull-down circuits according to an internal pull-down mode to acquire a second input voltage signal (at a second logic value) from the input pin. A selection of the operating mode of the MCU is then made based on the acquired first and second logic values.

Abstract: A single-layer Wide Angle Impedance Matching (WAIM) and method for using the same are described. In one embodiment, the antenna comprises: an aperture having a plurality of antenna elements operable to radiating radio-frequency (RF) energy; and a single-layer wide angle impedance matching (WAIM) structure coupled to the aperture to provide impedance matching between the antenna aperture and free space.

Abstract: A coupling device includes a plurality of couplers, a first coupled output port and a second coupled output port, wherein the plurality of couplers comprise a first coupler and a second coupler that are adjacent one another, and each of the first coupler and the second coupler comprises a main line and a subline, and for each of the first coupler and the second coupler: the subline includes a first section, a second section, and a third section, wherein the second section of the subline of the first coupler has a common segment with the first section of the subline of the second coupler.

Abstract: Systems for shielding bent signal lines provide ways to couple different antenna arrays for radio frequency (RF) integrated circuits (ICs) (RFICs) associated therewith where the antenna arrays are oriented in different directions. Because the antenna arrays are oriented in different directions, the antenna structures containing the antennas may be arranged in different planes, and signal lines extending therebetween may include a bend. To prevent electromagnetic interference (EMI) or electromagnetic crosstalk (EMC) from negatively impacting signals on the signal lines, the signal lines may be shielded. The shields may further include vias connecting the mesh ground planes and positioned exteriorly of the signal lines. The density of the vias may be varied to provide a desired rigidity in planes containing the antenna arrays while providing a desired flexibility at a desired bending location in the signal lines to help bending process accuracy.

Abstract: An antenna arrangement is provided that includes a patch radiator, a feed arrangement, for the patch radiator and a cavity for the feed arrangement. The feed arrangement includes a slot in a conductive layer located between the patch radiator and the cavity.

Abstract: A color changing television antenna with LED includes a casing, an antenna radiator in the casing, a coaxial cable situated at a rear end of the casing and connected to the antenna radiator. The casing contains an LED lamp, and a transparent display panel extending to the outside from the display panel. The part of the display panel inside the casing has a receiving slot for installing the LED lamp and allowing the LED lamp to project light onto a sidewall of the receiving slot. The display panel transmits the projected light by total reflection. A reflector is installed on a surface of the display panel for reflecting the light transmitted inside the display panel and forming a predetermined pattern. This television antenna can display a specific pattern and improve the display effect based on the principle of total reflection of the transparent display panel.

Abstract: An antenna array device and an antenna unit thereof are provided. The antenna unit includes an antenna structure and a molding support. The antenna structure includes a substrate and a plurality of patches that are formed on the substrate. The substrate has a plurality of channel holes penetrating there-through. The molding support is integrally formed on the substrate as a single one-piece structure. The molding support has a first stand, a second stand, and a plurality of connection portions that are formed in the channel holes to connect the first stand and the second stand. The first stand and the second stand are formed on two sides of the substrate, respectively.

Abstract: A system includes a mixer of a phase interpolator. The mixer includes a dynamic load whose output signal is coupled to a subsequent stage of the phase interpolator. The dynamic load is configured to provide an alternating current (AC) signal to the subsequent stage of the phase interpolator as input clock signals. The mixer further includes a static load whose output signal is coupled to the subsequent stage of the phase interpolator in parallel with the respective output signal line of the dynamic load. The static load configured to provide a direct current (DC) signal to the phase interpolator temporarily in replacement of the respective AC signals to prevent output signals of the subsequent stage of the phase interpolator from being unpredictable.

Abstract: An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.

Abstract: A steerable antenna comprising (1) a lower waveguide configured to direct radio frequency signals in a specific direction, (2) an upper waveguide positioned substantially parallel to the lower waveguide, wherein the upper waveguide is configured to direct the radio frequency signals in another direction substantially opposite to the specific direction, and (3) a plate coupled between the lower waveguide and the upper waveguide, wherein the plate includes one or more coupling elements that facilitate transferring the radio frequency signals between the lower waveguide to the upper waveguide. Various other apparatuses, systems, and methods are also disclosed.