Patents Examined by Jaweed A Abbaszadeh
  • Patent number: 11068036
    Abstract: A control method of a portable electronic device (PED) includes following steps. A trigger event is received. Next, an accelerator detects a first behavior of the PED and produces a first signal. If the first signal satisfies a first preset condition, the accelerator detects a second behavior of the PED and produces a second signal. If the second signal satisfies a second preset condition, the PED performs an action.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: July 20, 2021
    Assignee: PEGATRON CORPORATION
    Inventor: Shih-Hao Chen
  • Patent number: 11068040
    Abstract: In accordance with a first aspect of the present disclosure, a transponder is provided, comprising: digital logic for processing one or more portions of a data frame; a status detection unit configured to detect a status of a data frame reception or data frame transmission; a clock gating unit configured to apply clock gating to said digital logic in dependence on the status of said data frame reception or data frame transmission. In accordance with further aspects of the present disclosure, a corresponding method of operating a transponder is conceived, and a corresponding computer program is provided.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: July 20, 2021
    Assignee: NXP B.V.
    Inventors: Raghavendra Kongari, Shankar Joshi, Björn Rasmussen
  • Patent number: 11070200
    Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: Aaron Martin, Roger Cheng, Hari Venkatramani, Navneet Dour, Mozhgan Mansuri, Bryan Casper, Frank O'Mahony, Ganesh Balamurugan, Ajay Balankutty, Kuan Zhou, Sridhar Tirumalai, Krishnamurthy Venkataramana, Alex Thomas, Quoc Nguyen
  • Patent number: 11061802
    Abstract: A method of determining a time stamp for an event in a digital processing system, the method comprising the steps of: obtaining a coarse time stamp from a time stamp counter; obtaining timing correction data from one or more hardware components of the system; and adjusting the coarse time stamp value based on the timing correction data to provide a precision time stamp value.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: July 13, 2021
    Assignee: Zomojo PTY LTD
    Inventor: Matthew Chapman
  • Patent number: 11061457
    Abstract: Technology to dynamically share system power among charging ports of a multiport power delivery (PD) system is described. In one embodiment, a multiport PD system includes a master controller associated with a master port, and one or more slave controllers associated with one or more slave ports. The master controller determines a port connection status of a set of multiple ports. The port connection status indicates that multiple devices are connected. The master controller determines a power requirement of each of the devices. The master controller dynamically allocates a system power between each of the ports, independent of a connection sequence of the devices.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: July 13, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Debraj Bhattacharjee, Kailas Iyer, Palaniappan Subbiah, Subramanyam Sankaran, Anshul Gulati, Neel Karkhanis
  • Patent number: 11061692
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine if a wake event corresponds to a zero-power state of a computer operating system, determine if a run-time state is valid to wake the operating system from the zero-power state, and wake the operating system from the zero-power state to the run-time state if the run-time state is determined to be valid. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Michael Rothman, Vincent Zimmer
  • Patent number: 11061429
    Abstract: A technique for fine-granularity speed binning for a processing device is provided. The processing device includes a plurality of clock domains, each of which may be clocked with independent clock signals. The clock frequency at which a particular clock domain may operate is determined based on the longest propagation delay between clocked elements in that particular clock domain. The processing device includes measurement circuits for each clock domain that measure such propagation delay. The measurement circuits are replica propagation delay paths of actual circuit elements within each particular clock domain. A speed bin for each clock domain is determined based on the propagation delay measured for the measurement circuits for a particular clock domain. Specifically, a speed bin is chosen that is associated with the fastest clock speed whose clock period is longer than the slowest propagation delay measured for the measurement circuit for the clock domain.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: July 13, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Greg Sadowski, Shomit N. Das
  • Patent number: 11054885
    Abstract: A computing device, such as a multifunction printer, may be configured to supply electrical power to one or more external devices. The computing device may include a user interface that can display information to a user, informing the user of the electrical power being supplied to the one or more external devices and/or of the total amount of electrical power that is available to the one or more external devices. The user may use the user interface to adjust the amount of power being supplied to each of the external devices, and the computing device may store information indicating the user's adjusted power levels and use the stored information to control the amount of power supplied to the external devices.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: July 6, 2021
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Yasuhiro Shimamura
  • Patent number: 11054882
    Abstract: In an embodiment, a local throttling mechanism for the one or more processor cores may support one or more externally-triggered throttling mechanisms. An external source, such as a system-level power manager, may detect an energy-consumption state in the system as a whole and may trigger additional throttling in the processor core throttling mechanism. The externally-triggered throttling may temporarily increase throttling in the processor cores, in an embodiment, decreasing processor core energy consumption to account for the excess energy consumption in other parts of the system.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: July 6, 2021
    Assignee: Apple Inc.
    Inventor: Daniel U. Becker
  • Patent number: 11036270
    Abstract: Systems and methods for providing power to a home entertainment integrated circuit chip are disclosed. The home entertainment integrated circuit chip can operate in at least two power control modes: “power on” mode and “standby” mode. In power on mode, power is supplied to IC core module from a main power supply. The power supplied to the IC core module is isolated from power supplied to a standby island. Accordingly, during the second mode power is applied only to the standby power island through a regulator internal to the integrated circuit chip. The regulator is coupled to an external peripheral input/output (I/O) power supply that is independent of the main power supply.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: June 15, 2021
    Assignee: Entropic Communications, LLC
    Inventor: Branislav Petrovic
  • Patent number: 11029964
    Abstract: Approaches for configuring a system-on-chip (SOC) include generating component images for components of the SOC. A first component image is for a platform management controller, a second component image is for programmable logic, and a third component image is for a processor subsystem. The plurality of component images are assembled into a programmable device image, and the programmable device image is input to the platform management controller. The platform management controller is booted from the first component image, the programmable logic is configured with the second component image by the platform management controller in executing the first component image, and the processor subsystem is configured with the third component image by the platform management controller in executing the first component image.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: June 8, 2021
    Assignee: XLNX, INC.
    Inventors: Siddharth Rele, Shreegopal S. Agrawal, Kaustuv Manji, Aditya Chaubal
  • Patent number: 11025442
    Abstract: A method for a network apparatus to control power provision to a powered device is proposed. The network apparatus is configured for connection to the powered device, an electronic device, and a power supply device. The network apparatus permits transmission of electronic power provided by the power supply device to the powered device therethrough when the electronic device is communicatively connected to the network apparatus, and does not permit transmission of electronic power provided by the power supply device to the powered device therethrough when the electronic device is not communicatively connected to the network apparatus.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: June 1, 2021
    Assignee: YODA COMMUNICATIONS, INC.
    Inventor: Young-Lim Su
  • Patent number: 11023026
    Abstract: An integrated circuit includes: a first current detection circuit configured to, when a first enable signal is in an activated state, detect a current flowing between a first node and a second node, and generate an output signal, and when the first enable signal is in a deactivated state, stop a current detection operation; a first voltage detection circuit, which operates intermittently or operates continuously, that is configured to detect a voltage at the first node, and generate an output signal; and a control circuit that is configured to generate the first enable signal and supply the first enable signal to the first current detection circuit, and is configured to fetch the output signal of the first voltage detection circuit in a period other than the period in which the first enable signal transitions from a deactivated state to an activated state.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: June 1, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Kinya Matsuda
  • Patent number: 11010175
    Abstract: Circuitry comprises control circuitry to control an operating state of a data handling device of a set of two or more redundant data handling devices configured to perform identical data handling functions; the control circuitry being configured to control an operating state of the respective controlled data handling device as a state transition from a current operating state of that data handling device to a target operating state in response to the issue of a respective state change signal; the control circuitry comprising a detector responsive to issue of the state change signal in respect of a first threshold number representing some but not all of the data handling devices, to detect whether the state change signal is issued in respect of a further one or more of the devices so that a second threshold number of data handling devices is reached.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: May 18, 2021
    Assignee: ARM Limited
    Inventor: Julian Jose Hilgemberg Pontes
  • Patent number: 11009930
    Abstract: A universal serial bus (USB) hub includes detection circuits for a D? and a D+ connection of a USB port and a control circuit. The control circuit is configured to disable, detection circuits, respective impedances. After disabling the respective impedances, the USB hub is further configured to detect, at the detection circuits, respective values from the D+ connection and the D? connection. The USB hub is further configured to, based upon the respective values, switch the USB port between a device port configuration and a host port configuration.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: May 18, 2021
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Jeffrey Hunt, Andrew Rogers
  • Patent number: 11009938
    Abstract: In one embodiment, a system includes power management control that controls a duty cycle of a processor to manage power. The duty cycle may be the amount of time that the processor is powered on as a percentage of the total time. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. For example, the processor may be a graphics processing unit (GPU), and the period of time over which the duty cycle is managed may be a frame to be displayed on the display screen viewed by a user of the system.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: May 18, 2021
    Assignee: Apple Inc.
    Inventors: Patrick Y. Law, Robert A. Drebin, Keith Cox, James S. Ismail
  • Patent number: 11003460
    Abstract: A control method of a memory storage device is provided and includes: detecting a first signal stream controlled by a host system; executing a boot code according to the first signal stream and entering a boot code mode; and receiving a command from the host system in the boot code mode and not executing a firmware code stored in a rewritable non-volatile memory module in the memory storage device. According, operational flexibility of the memory storage device may be enhanced.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: May 11, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ming-Fu Lai, Ying-Fu Chao, Chao-Ta Huang, Chun-Yu Ling
  • Patent number: 11003238
    Abstract: A hierarchy of interconnected memory retention (MR) circuits detect a clock gating mode being entered at any level of an integrated circuit. In response, the hierarchy automatically transitions memory at the clock gated level and all levels below the clock-gated level from a normal operating state to a memory retention state. When a memory transitions from a normal operating state to a memory retention state, the memory transitions from a higher power state (corresponding to the normal operating state) to a lower power state (corresponding to the memory retention state). Thus, in addition to the dynamic power savings caused by the clock gating mode, the hierarchy of MR circuits automatically transitions the memory modules at the clock gated level and all levels below the clock gated level to a lower power state. As a result, the leakage power consumption of the corresponding memory modules is reduced relative to prior approaches.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: May 11, 2021
    Assignee: NVIDIA Corporation
    Inventors: Anand Shanmugam Sundararajan, Ramachandiran V, Abhijeet Chandratre, Lordson Yue, Archana Srinivasaiah, Sachin Idgunji
  • Patent number: 10997296
    Abstract: Operations include restoring a trusted system firmware state. A system stores a set of self-contained secure code in a secure code store. The system stores a set of operational code in an operational code store. The system executes the secure code or the operational code upon system start up, depending whether the system is configured in a secure mode, or in a normal operational mode. When the system is configured in secure mode, the system executes the secure code. In secure mode, the system also overwrites a current version of the operational code stored in the operational code store with a replacement version of the operational code referenced by the secure code. When the system is configured in normal operational mode, the system executes the operational code. During normal operation, the secure code store is electrically isolated.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: May 4, 2021
    Assignee: Oracle International Corporation
    Inventors: James A. Heck, Ralph P. Valentino, David W. Hartwell
  • Patent number: 10996730
    Abstract: An electronic device includes a power supply, a connector, a detector, and a switch. The connector is configured to be alternatively connectable in a first direction and in a second direction. The detector is configured to detect which of the first direction and the second direction the connector has been connected in. The switch is configured to switch a state of the electronic device between a first state to supply power to another device and to a second state to receive power from said another device. The switch is configured to switch the state of the electronic device to the first state or the second state according to a connection direction of the connector detected by the detector.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: May 4, 2021
    Assignee: Ricoh Company, Ltd.
    Inventor: Yoshitaka Kimura