Patents Examined by Jaweed A Abbaszadeh
  • Patent number: 11403112
    Abstract: An information processing apparatus according to one aspect of the present invention includes a main body and an operation device. The operation device executes an operating system (OS) and a program task operating independently of the OS. The program task is configured to start up earlier than the OS and to perform a part of a start up process required for starting up the operation device. When the main body and the operation device are started, the operation device starts executing the program task in addition to starting execution of the OS. In response to a completion of performing the part of the start up process, the program task transmits a ready state notification to the main body.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: August 2, 2022
    Assignee: Ricoh Company, Ltd.
    Inventor: Mami Arai
  • Patent number: 11397455
    Abstract: Examples are disclosed that relate to power supply devices and methods for managing DC power. In one example, a method comprises: providing DC power at a first voltage until determining that a standby time period has elapsed; determining that a load is connected to the power supply device; and based on determining that the standby time period has elapsed, entering a restricted power mode, wherein the restricted power mode comprises either: deactivating the DC power, or (1) providing the DC power at a second voltage until determining that a load detection time period has elapsed, (2) deactivating the DC power after determining that the load detection time period has elapsed, and (3) repeating (1) and (2) until determining that the load is no longer connected to the power supply device.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 26, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chee Kiong Fong, Geoffrey Jason Shew, Gary Alan Tornquist, Edward C. Giaimo, III, Richard F. Johnson, Tim R. Calland
  • Patent number: 11399344
    Abstract: A method and apparatus of a device that manages system performance by controlling power state based on information related to I/O operations is described. The device collects historical I/O information. The historical I/O information may include the number of I/O operations over a sample period of time and the inter-arrival time between I/O operations. The device further receives information related to a current I/O operation. The information of the current I/O operation may include direction, size, quality of service, and media type of the I/O operation. The device determines a power state based on the historical I/O information and the information relative to the current I/O operation to reduce power consumption while improving system efficiency and maintaining an acceptable level of system performance. The device further applies the determined power state. Other embodiments are also described and claimed.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: July 26, 2022
    Assignee: Apple Inc.
    Inventor: Derek R. Kumar
  • Patent number: 11392702
    Abstract: Described herein is a device (e.g., IoT device) having bootstrap code that communicates with a secure global registry (e.g., private distributed shared blockchain database). The bootstrap code of the device uses a globally unique device identifier of the device to the secure global registry. The bootstrap code receives information from the secure global registry which the bootstrap code uses to obtain information to connect to a cloud-based endpoint. The bootstrap code can download an appropriate software development kit (SDK) associated with the particular cloud based, at least in part, upon the received information. The device can be registered in the secure global registry by creating a globally unique identifier for the device. An initial entry can be created in the secure global registry comprising the globally unique identifier, with the secure global registry stores current cloud-based endpoint information, if any, for the device.
    Type: Grant
    Filed: March 17, 2019
    Date of Patent: July 19, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Balendran Mugundan, Affan Arshad Dar, Anush Prabhu Ramachandran, Raimundo Robledo Pontes Filho, Rajeev Mandayam Vokkarne
  • Patent number: 11392391
    Abstract: A BIOS image can be selectively updated. An image loader of the BIOS can be configured to detect whether a BIOS image to be loaded includes a selective update capability field, and if so, employ a value defined in the selective update capability field to determine whether an updated BIOS image exists. When an updated BIOS image exists, the image loader can load the updated BIOS image rather than the BIOS image. In this way, an individual BIOS image can be selectively updated without needing to update the entire BIOS.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: July 19, 2022
    Assignee: Dell Products L.P.
    Inventors: Sumanth Vidyadhara, Shekar Babu Suryanarayana
  • Patent number: 11392167
    Abstract: A computing device may perform a method that includes determining whether internal time reference data is available while booting the computing device. When the internal time reference data is unavailable, the device clock is set to a default time setting. However, when the internal time reference data is available while booting the computing device, the method includes searching the internal time reference data for a most recent time reference, and setting the device clock to a current time setting based on the most recent time reference.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: July 19, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Dennis R. LaCroix
  • Patent number: 11385703
    Abstract: A semiconductor device selects one start sequence of the normal start and the low-power-consumption start based on the determination result of the determination circuit. According to the configuration, the operation in the start sequence from the power supply input to the processor operation start can be selected from the operation in which the instantaneous current is suppressed and the high-speed operation based on the supplied power supply.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: July 12, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuaki Gemma
  • Patent number: 11374486
    Abstract: A power supply having at least one PMIC provides flexible control to the power manage systems. The PMIC has an enable pin configured to receive a control signal, and a clock pin configured to generate and/or receive a series of clock pulses, so as to facilitate the operation of the PMIC.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: June 28, 2022
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Bo Zhou, Ming Lu, Pengjie Lai, Jian Jiang
  • Patent number: 11372442
    Abstract: In the present invention, control feasibility in a vehicle control system architecture is efficiently determined by performing determination based on control feasibility in a physical element based on a converted parameter when a logical architecture is arranged in a physical architecture. The present invention includes: an arrangement unit 101 that arranges a logical architecture 601, which includes a linkage of each of logical functions and an execution time constraint of the linkage, in a physical architecture 300; a delay time calculation unit 104 that calculates a processing delay time based on a converted parameter when the logical architecture 601 is arranged in the physical architecture 300; and a verification unit 102 that verifies whether a total of the processing delay time satisfies the execution time constraint.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: June 28, 2022
    Assignee: HITACHI ASTEMO, LTD.
    Inventors: Satoshi Otsuka, Kohei Sakurai, Fumio Narisawa
  • Patent number: 11372471
    Abstract: A system circuit board configured to be supplied by at least one power supply unit, with an operating voltage in an operating state and a stand-by voltage in at least one stand-by state, the system circuit board includes at least one connection device for at least one extension card, wherein the connection device is configured to provide at least one first card voltage on the basis of the operating voltage; at least one switching element arranged on the system circuit board and configured to disconnect the at least one connection device from the operating voltage; and a control device arranged on the system circuit board, and configured to identify a type of a connected power supply unit and send a switching signal to the switching element depending on the identified type.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: June 28, 2022
    Assignee: Fujitsu Technology Solutions Intellectual Property GmbH
    Inventors: Rainer Staude, Rudolf Häußermann, Waldemar Felde, Andreas Maier
  • Patent number: 11366506
    Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: June 21, 2022
    Assignee: Intel Corporation
    Inventors: Jianwei Dai, David Pawlowski, Adwait Purandare, Ankush Varma
  • Patent number: 11366505
    Abstract: Methods, systems, and devices for predictive power management are described. Correlations may be identified between a set of commands performed at the memory device and oscillating voltage patterns, or a resonance frequency, or both. Voltages may be monitored by the memory device and be compared to the identified voltage pattern to mitigate undesirable oscillating voltages and resonance frequency.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: June 21, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Fuad Badrieh, Baekkyu Choi, Thomas H. Kinsley
  • Patent number: 11360542
    Abstract: This disclosure provides a method and an apparatus for operating a processor in an electronic device. The method includes identifying an average throughput for a first set of subframes, predicting a load of the processor for a second set of subframes based on the identified average throughput, determining an operating frequency of the processor for the second set of subframes based on the predicted load, and operating the processor on the determined operating frequency for the second set of subframes.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: June 14, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mahantesh Kothiwale, Satyam Namdeo, Yunas Rashid, Srinivasa Rao Kola, Manjunath Jayram
  • Patent number: 11353944
    Abstract: Methods, systems, and devices for predictive power management are described. Correlations may be identified between a set of commands performed at the memory device and oscillating voltage patterns, or a resonance frequency, or both. Voltages may be monitored by the memory device and be compared to the identified voltage pattern to mitigate undesirable oscillating voltages and resonance frequency.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Fuad Badrieh, Baekkyu Choi, Thomas H. Kinsley
  • Patent number: 11354135
    Abstract: A computing device that implements a multithread parallel processing computing platform prior to initialization of system memory is provided. To implement this platform, the computing device executes enhanced firmware that defines a plurality of application processors (APs) under the control of a boot-strap processor (BSP). The BSP preserves backward compatibility of the APs by configuring cross-reference circuitry (e.g., a programmable attribute map) to reroute memory access requests generated by the APs that are addressed to a wakeup buffer to a redirected memory address. Memory at the redirected memory address stores AP initialization instructions and instructions to retrieve and process early stage process instructions stored elsewhere (e.g., in fast access cache memory). The APs, in parallel, execute the initialization instructions and the early stage process instructions stored in cache to complete an early stage process, such as memory training.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: June 7, 2022
    Assignee: INTEL CORPORATION
    Inventors: Zhiqiang Qin, Tao Xu, Qing Huang
  • Patent number: 11347295
    Abstract: Methods and system for power management of computing resources supporting one or more virtual machines involves grouping the plurality of virtual machines into a plurality of groups. The grouping can comprise assigning each of the plurality of virtual machines to one or more of the plurality of groups based on virtual machine functionality. For each group, a further determination is made as to whether the level of activity is indicative of an idle state. Upon determining that the level of activity associated with a group is indicative of an idle state, that group of virtual machines is instructed to enter a low power mode.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: May 31, 2022
    Assignee: Citrix Systems, Inc.
    Inventors: Nitin D. Mehta, Leo C. Singleton, IV, Kevin Woodmansee, Jitendra Deshpande, Harsh Murarka
  • Patent number: 11347290
    Abstract: Power monitor information in an information handling system may be adjusted based on a battery voltage to account for a battery discharge state. The power monitor information may be scaled higher when the battery voltage is low to encourage the system to throttle and decrease power consumption. This adjustment increases the likelihood that the battery remains within safe operating limits.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: May 31, 2022
    Assignee: DELL PRODUCTS L.P.
    Inventors: Mohammed Hijazi, Merle J. Wood, III, Christian L. Critz, Chin-Jui Liu
  • Patent number: 11348909
    Abstract: Methods and apparatus to implement efficient memory storage in multi-die packages are disclosed. An example multi-die package includes a multi-die stack including a first die and a second die. The second die is stacked on the first die. The multi-die package further includes a third die adjacent the multi-die stack. The multi-die package also includes a silicon-based connector to communicatively couple the multi-die stack and the third die. The silicon-based connector includes at least one of a logic circuit or a memory circuit.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Maruti Gupta Hyde, Nageen Himayat, Linda Hurd, Min Suet Lim, Van Le, Gayathri Jeganmohan, Ankitha Chandran
  • Patent number: 11340671
    Abstract: A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: May 24, 2022
    Assignee: Google LLC
    Inventors: Shailendra Desai, Mark Pearce, Amit Jain, Jaymin Patel
  • Patent number: 11340691
    Abstract: A heat dissipation apparatus with energy-saving effect is coupled to an operation unit, and the heat dissipation apparatus includes a control unit and a drive circuit. The control unit determines whether the operation unit enters an energy-saving mode according to a first signal provided by the operation unit. The control unit shields a plurality of second signals provided to the drive circuit according to the energy-saving mode. The drive circuit does not drive the heat dissipation unit and the heat dissipation unit enters an inertia deceleration.
    Type: Grant
    Filed: April 18, 2020
    Date of Patent: May 24, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chia-Feng Wu, Po-Hui Shen, Chien-Sheng Lin, Chun-Chieh Tsai, Chia-Wei Hsu, Rou-Sheng Wang