Abstract: Controlling a vehicle comprises: providing, from an activation port, an activation signal for activating control of at least one of one or more electronically controllable devices during a high-speed activation time interval; and managing power consumed by an integrated circuit that includes two or more processor cores during the high-speed activation time interval. The managing includes: receiving the activation signal from the activation port, in response to the activation signal, executing at least a portion of stored code by a first subset of fewer than all of the processor cores at a first power level, and after the high-speed activation time interval, executing at least a portion of the stored code by a second subset of one or more of the processor cores at a second power level lower than the first power level.

Abstract: An information processing apparatus according to an embodiment of the present disclosure includes: a processor including a first data processor that is configured to perform a piece of first data processing on the basis of a piece of first data to thereby generate a piece of second data; a selector that selects one piece of data from among a plurality of pieces of data including the piece of first data and the piece of second data; an arithmetic processor that is configured to selectively perform one of a plurality of pieces of arithmetic processing, and performs a piece of arithmetic processing selected from among the plurality of pieces of arithmetic processing on the basis of the piece of data selected by the selector; and a supply section that controls supply of electric power to the first data processor in accordance with the piece of data selected by the selector from among the plurality of pieces of data.

Abstract: Systems and devices can include power management circuitry to manage the entry and exit of active state power management (APSM) link states, such as the transition between an active (L0) state and a low power state (e.g., L1). The power management circuitry can cause a downstream component to initiate an ASPM link state change negotiation based on an ASPM link state change condition being met. An ASPM event analysis logic can identify and track events that occur proximate in time to the ASPM link state change and can correlate the occurrences of the event with ASPM link state changes. An ASPM policy tuning logic can use a correlation between the occurrences of the event and ASPM link state changes to adjust or tune the ASPM link state change condition.

Abstract: In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.

Abstract: A dynamic peak power management system may prevent brownouts while improving performance and user experience compared to conventional techniques. A current threshold may be set below the maximum current capability (Imax) of a battery. If the current drawn from the battery exceeds the current threshold repeatedly, then system components may be throttled to decrease their peak power usage. If the current drawn from the battery stays below the current threshold for some time, then system components may be unthrottled to improve performance. This dynamic adaptable technique for managing peak power does not unnecessarily sacrifice performance by preemptively throttling system components to avoid the rare worst-case scenario where power spikes of system components perfectly align in time.

Abstract: A scheme is provided for a processor to measure or estimate the dynamic capacitance (Cdyn) associated with an executing application and take a proportional throttling action. Proportional throttling has significantly less impact on performance and hence presents an opportunity to get back the lost bins and proportionally clip power if it exceeds a specification threshold. The ability to infer a magnitude of power excursion of a power virus event (and hence, the real Cdyn) above a set power threshold limit enables the processor to proportionally adjust the processor operating frequency to bring it back under the limit. With this scheme, the processor distinguishes a small power excursion versus a large one and reacts proportionally, yielding better performance.

Abstract: An information processing apparatus and an information processing method capable of fulfilling an image processing function expected in a selected power control mode are provided. The information processing apparatus includes a first processor, a second processor, and a power control unit that determines one power control mode from among a plurality of stages of power control modes different in rated power, and controls power consumption of the first processor and the second processor in the determined power control mode, wherein the power control unit stops an operation of the second processor in response to the determined power control mode being a low power control mode which is a power control mode with the rated power lower than predetermined rated power.

Abstract: A memory device including a receiving circuit is provided. The receiving circuit of the memory device includes a first path receiving a received signal and outputting the received signal directly as a first corrected signal in a current clock signal, a second path holding or tracking the received signal and outputting a second corrected signal in the current clock signal, wherein the second corrected signal is held in a previous clock signal, a summing circuit summing the first corrected signal and the second corrected signal and outputting a summed received signal, and a decision feedback equalizer comparing the summed received signal with a reference signal to decide equalized data and outputting the equalized data in the current clock signal.

Abstract: A first communication device performs a handshaking procedure with a second communication device, the handshaking procedure associated with transitioning from an active mode to a low power mode. The first communication device transmits data and/or idle symbols to the second communication device i) after completion of the handshake procedure, and ii) at least until the earlier of a) a time period expiring, and b) determining that the second communication device quieted a transmitter of the second communication device. The first communication device transitions to the low power mode in connection with the handshaking procedure.

Abstract: Systems, apparatuses and methods may provide for technology that detects an over current condition associated with a voltage regulator in a computing system, identifies a configurable over current protection policy associated with the voltage regulator, and automatically takes a protective action based on the configurable over current protection policy. In one example, the protective action includes one or more of a frequency throttle of a processor coupled to the voltage regulator in isolation from one or more additional processors in the computing system, a deactivation of the processor in isolation from the one or more additional processors, an issuance of a virtual machine monitor notification, an issuance of a data center fleet manager notification, or an initiation of a migration of a workload from the processor to at least one of the additional processor(s).

Abstract: Techniques described herein relate to a method for optimizing power for a computer vision environment. The method includes obtaining, by a computer vision (CV) manager, an initial power optimization request associated with a CV workload; in response to obtaining the initial power optimization request: obtaining CV workload information associated with the CV workload; obtaining first CV environment configuration information associated with the power optimization request; generating a power optimization report based on the first CV environment configuration information and the CV workload information using a power optimization model; and initiating performance of the CV workload in a CV environment based on the power optimization report.

Abstract: A computing system may implement a basic input/output system (BIOS) update method. The BIOS also includes identifying an installed central processing unit (CPU) of a computer system coupled to a BIOS chipset, selecting CPU firmware corresponding to the installed CPU from a plurality of CPU platform firmware stored on a first memory, and loading the CPU firmware into a shared portion of a second memory coupled to the BIOS chipset, where the shared portion of the second memory is configured to store the CPU firmware as secondary CPU firmware.

Abstract: Implementations of this application provide a method and an apparatus for controlling a voltage of a power supply of a data processing device and a data processing device. The method includes: determining a computing power ratio of the data processing device based on an actual computing power and a theoretical computing power of the data processing device; generating a power supply control instruction based on a result of comparison between the computing power ratio and a predetermined threshold; and controlling an output voltage of the power supply of the data processing device based on the power supply control instruction. According to the implementations of this application, the output voltage of the power supply is controlled according to the computing power ratio, and a good compromise can be obtained between the power consumption loss and the computing power of the data processing device.

Abstract: Methods, systems, and devices for providing computer implemented services using managed systems are disclosed. To provide the computer implemented services, the managed systems may need to operate in a predetermined manner conducive to, for example, execution of applications that provide the computer implemented services. Similarly, the managed system may need access to certain hardware resources (e.g., and also software resources such as drivers, firmware, etc.) to provide the desired computer implemented services. To improve the likelihood of the computer implemented services being provided, the managed systems may be managed using a subscription based model. The subscription model may utilize a highly accessible service to obtain information regarding desired capabilities (e.g., a subscription) of a managed system, and use the acquired information to automatically configure and manage the features and capabilities of the managed systems by powering and depowering select components.

Abstract: A USB slave device and its power quality testing method, where the USB slave device is preset to enable only minimum functions required for the power quality testing method. When the USB slave device is connected to the USB power supply device, the power quality testing is activated. If the USB slave device is not rebooted after a period of time, the power quality testing is determined to be passed and fully functionality of the USB salve device is activated.

Abstract: An electronic device includes a semiconductor memory device configured to store process information and to output the process information to the outside; and a host configured to read the process information from the semiconductor memory device, and to select one of a plurality of operation modes depending on the process information so as to be set to an operation mode of the semiconductor memory device. The plurality of operation modes may define one or more of power consumption of the semiconductor memory device or a response characteristic of the semiconductor memory device.

Abstract: A new peripheral component interconnect express (PCIe) link state can enhance power saving capabilities of a PCIe link operating in a flow control unit (FLIT) mode. A device can operate a data link with a host in a FLIT mode using fixed-sized packets, the data link being in a partial width link state (PLS) in which a first set of lanes of the data link are in an electrical idle state and a second set of lanes of the data link are in an active state available for data traffic with the host. The device can transition one or more lines of the second set of lanes from the PLS to a partial width standby link state (PSLS) in which the one or more lines of the second set of lanes are in a standby state that has lower power consumption than the active state.

Abstract: Methods and structures are described for detecting clock anomalies, including anomalies in which the clock oscillates at a faster than expected rate or exhibits a shorter than expected clock phase instance. Example methods include starting a timer responsive to the start of a clock phase, wherein the timer duration is shorter than an expected duration of the clock phase. If the clock phase ends before the timer expires, a fast clock detection signal is asserted. Example structures include fast clock detection logic coupled to a clock signal. The logic includes a timer, circuitry to start the timer responsive to the clock signal entering a monitored phase, and error detection circuitry to assert a fast clock detection output if the monitored phase ends before the timer expires. In some embodiments, the timer duration may be based on a measured duration of a previous clock phase.

Abstract: An information handling system includes a memory, and a basic input/output system (BIOS). The BIOS receives a request to map multiple processor cores to multiple integrated memory controllers of a multiple core processor. In response to the reception of the request, the BIOS calculates a different latency for each of the processor cores. Based on the calculated different latency for each of the processor cores, the BIOS assigns mapping priority levels to the processor cores of the multiple core processor. Based on the mapping priority levels, the BIOS maps each of the processor cores to an associated one of the integrated memory controllers. The BIOS stores the map of the processor cores in the memory.

Abstract: A power management integrated circuit (PMIC) includes voltage regulators, a conversion circuit, a measurement cycle controller, an oscillator, and a control logic. The voltage regulators generate regulator voltages. The conversion circuit converts analog signals indicating load currents of the voltage regulators to generate digital signals corresponding to the load currents. The measurement cycle controller operates in response to a first clock signal having a first frequency and generates an oscillation enable signal that is activated during a measurement period. The oscillator generates a second clock signal having a second frequency higher than the first frequency in response to the oscillation enable signal. The control logic operates in response to the second clock signal and generates power information, indicating power consumed by the load currents during the measurement period, using the digital signals.