Abstract: An apparatus including a printed circuit board (PCB) including a sense resistor; and an integrated circuit (IC) mounted on the PCB, wherein at least a portion of the IC draws current from a power rail, wherein the sense resistor is coupled between the power rail and the IC, wherein the sense resistor is configured to produce a sense voltage in response to the current drawn by the at least portion of the IC, and wherein the IC includes a current sensor configured to generate a signal indicative of the current drawn by the at least portion of the IC based on the sense voltage.

Abstract: The present disclosure discloses a power management circuit, a chip and an upgrade method therefor, and a server. In the circuit, one terminal of a micro controller unit is connected to a control board and a processor of the chip, and the other terminal of the micro controller unit is connected to a power management integrated circuit unit, a voltage conversion unit, and a voltage regulator unit. The micro controller unit receives operation instructions sent by the control board and the processor, stores the operation instructions, reads a power-on/off operation instruction in the operation instructions that is sent by the control board, and sends the power-on/off operation instruction to the power management integrated circuit unit to enable the power management integrated circuit unit performs corresponding control on the voltage conversion unit and the voltage regulator unit to complete a power-on/off operation on the processor.

Abstract: A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

Abstract: Methods and apparatus to provide power management for multi-die stacks using artificial intelligence are disclosed. An example integrated circuit (IC) package includes a computer processor unit (CPU) die, a memory die, inference engine circuitry within the CPU die, the inference engine circuitry to infer, based on a first machine learning model, a workload for at least one of the CPU die or the memory die, and power management engine circuitry within the CPU die, the power management engine circuitry distinct from the inference engine circuitry, the power management engine circuitry to adjust, based on a second machine learning model different than the first machine learning model, operational parameters associated with the at least one of the CPU die or the memory die, the inferred workload to be an input to the second machine learning model.

Abstract: The present disclosure provides a power allocating system, including adapters and an electronic device. Each of the adapters includes a processor. The electronic device includes a controller. The controller obtains rated information and current output information from each of the processors to calculate an output utilization rate of each of the adapters. The controller transmits at least one adjusting signal to at least one of the processors according to the output utilization rates to adjust the output utilization rate of the adapters.

Abstract: A powering patch panel system includes a patch panel device coupled to a power source, and including a first port that is coupled to a networking device via a first cable and a second port that is coupled to the powered device via a second cable. The patch panel device receives data that is directed to the powered device from the networking device through the first port and via the first cable, and receives power from the power source. The patch panel device then transmits both the data and a subset of the power through the second port and via the second cable to the powered device. The first port may be provided by optical-fiber-based port and the first cable may be provided by an optical-fiber-based cable, while the second port may be provided by a hybrid conductive-material/optical-fiber-based port and the second cable may be provided by a hybrid conductive-material/optical-fiber-based cable.

Abstract: Methods and systems for power management are disclosed. The disclosed methods and system for power management may reduce the likelihood of a data processing system failing to meet power budget or other types of goals regarding power consumption, use, and/or provisioning. To reduce the likelihood of the data processing system failing to meet power related goals, the data processing system may include two power managers. An integrated power manager may manage power consumption based on a current-based, fast changing representation of the quantity of power being supplied by the power supplies. In contrast, a system power manager may manage power consumption based on digital representations of the power supplied by the power supplies, which may refresh the digital representations less quickly than the rate at which the analog current based representation is refreshed.

Abstract: An apparatus includes a power management integrated circuit (PMIC) and a power translator component coupled to the PMIC. The power translator component supplies power to the PMIC. The power translator component can further receive, from the PMIC, an indication that the PMIC has experienced a thermal event and responsive to receipt of the indication that the PMIC has experienced the thermal event, prevent powering of the PMIC.

Abstract: A scheme to improve performance of power-constrained computers, comprising a heterogeneous mix of compute elements, by dynamically reacting to changes in the switching capacitance that present workload induces in each heterogeneous compute element and learning the coefficients of a power-frequency model for each compute element for the present workload. At each time step, the scheme forecasts a maximum frequency that the compute element can run at without exceeding an input power limit for a given workload. The scheme rapidly re-learns coefficients of the power model and rapidly adapts the frequency as the workload's characteristics shift ensuring that compute elements run at the maximum frequency they can while not exceeding the input power limit.

Abstract: An information handling system is configured to support first and second boot sequences, which invokes first and second bootloaders respectively. The bootloaders may be stored in an NVMe storage boot partition. Each bootloader may be associated with a corresponding encryption key generated by a trusted platform module, which may seal the first and second keys in accordance with one or more measurements taken during the respective boot sequences. The system determines whether a boot sequence in progress comprises is to invoke the first or second bootloader. The system then unseals the appropriate encryption key to access the appropriate bootloader. The first bootloader may be a host OS bootloader and the second bootloader may be for a recovery resource invoked when the host OS fails to load. The recovery resource may enables BIOS to connect to a remote store and download an image via a HTTP mechanism.

Abstract: A first communication device performs a handshaking procedure with a second communication device, the handshaking procedure associated with transitioning from an active mode to a low power mode. The first communication device transmits data and/or idle symbols to the second communication device i) after completion of the handshake procedure, and ii) at least until the earlier of a) a time period expiring, and b) determining that the second communication device quieted a transmitter of the second communication device. The first communication device transitions to the low power mode in connection with the handshaking procedure.

Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.

Abstract: A direct current (DC) power distribution system is provided. The system includes a passive splitter and an active splitter. The passive splitter includes an input port that is configured to receive a first DC power input and multiple output ports that are configured to provide a first DC power outputs to corresponding ones of multiple power only devices. The active splitter includes an input port that is configured to receive a second DC power input and network data corresponding to at least one network communications data channel and multiple output ports that are configured to provide second DC power outputs and network communications data to corresponding power and/or data devices.

Abstract: In a method of operating a system-on-chip (SOC), the SOC includes a plurality of processor cores. An operating frequency of the plurality of processor cores is set to a first operating frequency based on permitted power consumption of the SOC and an operating status of the plurality of processor cores. The first operating frequency is within a maximum operating frequency of the plurality of processor cores. At least one of the plurality of processor cores performs at least one processing operation based on the first operating frequency. When present power consumption of the SOC is determined as exceeding the permitted power consumption, a warning signal is activated, and a first control operation for reducing the present power consumption is performed immediately thereafter.

Abstract: A method and system for intelligent power distribution management. Specifically, the disclosed method and system propose allocating (and deallocating) reserve or supplemental electrical power to host devices dynamically based on intelligent analyses of host device telemetry including, but not limited to, workload criticality, workload computing resource utilization, hardware configuration metadata, various operational parameters describing host device state, and measurements (as well as other information) pertinent to electrical power usage.

Abstract: Resource access control in a system-on-chip (“SoC”) may employ an agent executing on a processor of the SoC and a trust management engine of the SoC. The agent, such as, for example, a high-level operating system or a hypervisor, may be configured to allocate a resource comprising a memory region to an access domain and to load a software image associated with the access domain into the memory region. The trust management engine may be configured to lock the resource against access by any entity other than the access domain, to authenticate the software image associated with the access domain, and to initiate booting of the access domain in response to a successful authentication of the software image associated with the access domain.

Abstract: A method is provided in one example embodiment and includes storing secure boot variables in a baseboard management controller; and sending the secure boot variables to a basic input/output system (BIOS) during a power on self-test, where the BIOS utilizes the secure boot variables during runtime to authenticate drivers and an operating system loader execution. In particular embodiments, the secure boot variables may be included in a white list, a black list, or a key list and, further, stored in erasable programmable read only memory.

Abstract: Apparatus, method, and machine-readable medium to provide performance state matching between source and target processors based on inter-processor interrupts. An exemplary apparatus includes a target processor to execute a receiving task at a first performance level and a source processor to execute a sending task at a second performance level higher than the first performance level. The sending task is to store interrupt routing data indicating a pairing between the sending task and the receiving task into a memory location and that the sending task is to dispatch work to be processed by the receiving task. The apparatus further includes a performance management unit to detect the pairing between the sending task and the receiving task based on the interrupt routing data and responsively adjust the performance level of the target processor from the first performance level to the second performance level based, at least in part, on the pairing.

Abstract: Controlling a vehicle comprises: providing, from an activation port, an activation signal for activating control of at least one of one or more electronically controllable devices during a high-speed activation time interval; and managing power consumed by an integrated circuit that includes two or more processor cores during the high-speed activation time interval. The managing includes: receiving the activation signal from the activation port, in response to the activation signal, executing at least a portion of stored code by a first subset of fewer than all of the processor cores at a first power level, and after the high-speed activation time interval, executing at least a portion of the stored code by a second subset of one or more of the processor cores at a second power level lower than the first power level.

Abstract: A power distribution circuit for providing electric power from a plurality of power supplies to a plurality of loads comprises a combiner of power outputs of the power supplies to provide power at a given voltage to a plurality of hot swap modules that are each electrically connected to the combiner and to a power input of a corresponding load. Each hot swap module verifies one or more conditions selected from the given voltage being at least equal to a minimum voltage threshold, the given voltage not exceeding a maximum voltage threshold, and a current consumed by the load not exceeding a maximum current threshold. Each hot swap module delivers power to the power input of the corresponding load when all selected conditions are met and isolates the power input of the corresponding load from the power supplies when any one of the selected conditions is not met.