Abstract: Resource access control in a system-on-chip (“SoC”) may employ an agent executing on a processor of the SoC and a trust management engine of the SoC. The agent, such as, for example, a high-level operating system or a hypervisor, may be configured to allocate a resource comprising a memory region to an access domain and to load a software image associated with the access domain into the memory region. The trust management engine may be configured to lock the resource against access by any entity other than the access domain, to authenticate the software image associated with the access domain, and to initiate booting of the access domain in response to a successful authentication of the software image associated with the access domain.

Abstract: Apparatus, method, and machine-readable medium to provide performance state matching between source and target processors based on inter-processor interrupts. An exemplary apparatus includes a target processor to execute a receiving task at a first performance level and a source processor to execute a sending task at a second performance level higher than the first performance level. The sending task is to store interrupt routing data indicating a pairing between the sending task and the receiving task into a memory location and that the sending task is to dispatch work to be processed by the receiving task. The apparatus further includes a performance management unit to detect the pairing between the sending task and the receiving task based on the interrupt routing data and responsively adjust the performance level of the target processor from the first performance level to the second performance level based, at least in part, on the pairing.

Abstract: A method is provided in one example embodiment and includes storing secure boot variables in a baseboard management controller; and sending the secure boot variables to a basic input/output system (BIOS) during a power on self-test, where the BIOS utilizes the secure boot variables during runtime to authenticate drivers and an operating system loader execution. In particular embodiments, the secure boot variables may be included in a white list, a black list, or a key list and, further, stored in erasable programmable read only memory.

Abstract: Controlling a vehicle comprises: providing, from an activation port, an activation signal for activating control of at least one of one or more electronically controllable devices during a high-speed activation time interval; and managing power consumed by an integrated circuit that includes two or more processor cores during the high-speed activation time interval. The managing includes: receiving the activation signal from the activation port, in response to the activation signal, executing at least a portion of stored code by a first subset of fewer than all of the processor cores at a first power level, and after the high-speed activation time interval, executing at least a portion of the stored code by a second subset of one or more of the processor cores at a second power level lower than the first power level.

Abstract: A power distribution circuit for providing electric power from a plurality of power supplies to a plurality of loads comprises a combiner of power outputs of the power supplies to provide power at a given voltage to a plurality of hot swap modules that are each electrically connected to the combiner and to a power input of a corresponding load. Each hot swap module verifies one or more conditions selected from the given voltage being at least equal to a minimum voltage threshold, the given voltage not exceeding a maximum voltage threshold, and a current consumed by the load not exceeding a maximum current threshold. Each hot swap module delivers power to the power input of the corresponding load when all selected conditions are met and isolates the power input of the corresponding load from the power supplies when any one of the selected conditions is not met.

Abstract: The present invention provides a processing circuit, a method, and an electronic device for multiple power supply ports. The processing circuit includes N control modules and a bus. Each control module is correspondingly connected to a power supply port. The communication interface of each control module is connected to the bus. The bus is a one-wire bus and is connected to a power line ground through a resistor. The control modules transmit value signals to the bus. The varied range of a first physical quantity of a bus signal carried by the bus is related to first physical quantities or second physical quantities of all target signals transmitted to the bus. The control module detects the first quantity of the bus signal through the communication interface and adjusts the operating parameter of the connected power supply port according to the varied range of the detected first physical quantity.

Abstract: An Ethernet power supply device is provided. The Ethernet power supply device includes a first switch, a second switch, and a processor. When the first switch detects that there is no adapter power supply, the first switch generates a first power supply according to a first network power from a first Ethernet network connector port. When the second switch detects that there is no adapter power supply, the second switch generates a second power supply according to a second network power from the second Ethernet network connector port. When there is no adapter power supply and the first power supply and the second power supply are at the same power level, the processor provides a first control signal to control the first switch to provide the first power supply to a power output terminal as an output power supply.

Abstract: This application relates to apparatus and methods for booting servers, such as cloud datacenter compute servers. The servers may execute one or more hypervisors, such as stateless hypervisors, with each hypervisor supporting one or more virtual machines. In some examples, each of a plurality of servers are configured to boot from a network. The compute servers may obtain an IP address identifying a location of hypervisor bootable images. Upon a reboot, the servers may request and obtain a hypervisor bootable image from the IP address. The servers may execute the hypervisor bootable image to run a hypervisor. In some examples, the servers also obtain virtual machine images from the network. One or more hypervisors executing on each server may obtain, and execute, one or more of the virtual machine images to run one or more virtual machines.

Abstract: In an example, a computing device includes a non-volatile storage device to store a basic input/output system (BIOS) variable. Further, the computing device includes a BIOS. During a boot process of the computing devices, the BIOS may read the BIOS variable from the non-volatile storage device. Further, the BIOS may detect that an application is to be deployed in the computing device based on the BIOS variable. Furthermore, the BIOS may load an application package from the non-volatile storage device into a volatile storage device and build an advanced configuration and power interface (ACPI) data structure with the application package loaded in the volatile storage device. Further, the BIOS may deploy the application using the ACPI data structure.

Abstract: A power saving system of a battery charger is provided. A control terminal of a first transistor receives a wake-up signal. A counter is connected to a first terminal of the first transistor. The counter determines whether or not a working period of the wake-up signal from the first transistor is larger than a time threshold to output a counting signal. When the counting signal indicates that the working period of the wake-up signal is not larger than the time threshold, the counter and electronic components of an electronic device are turned off, thereby saving power of a battery. When the counting signal indicates that the working period of the wake-up signal is larger than the time threshold, the electronic device is switched from a power saving mode to a normal operation mode. In the normal operation mode, the battery can supply power to the electronic device.

Abstract: A boot Read-Only Memory (ROM) update method and a boot-up method of an embedded system are provided. The boot Read-Only Memory (ROM) update method of an embedded system including a memory and a ROM. The memory includes a user data area and a boot ROM area that includes a first area and a second area. The ROM copies a first boot code from the boot ROM area during boot-up. The boot ROM update method includes writing a second boot code to the second area in response to a first ROM update command. The second boot code includes a second boot ROM image and a second signature for the second boot ROM image. The method also includes verifying validity of the second signature and, if the second signature is valid, swapping the first area and the second area. The first boot code is disposed in the first area and includes a first boot ROM image and a first signature for the first boot ROM image.

Abstract: Methods, systems, and apparatus, including computer-readable media, for environment monitoring and management. In some implementations, information indicating a planned usage level for usage of cloud computing services is accessed by a group of multiple computing environments over a period of time. Usage of cloud computing services is monitored for the group of multiple computing environments. A usage measure indicating an amount of usage of cloud computing services by the group of multiple computing environments is generated over the period of time. A cloud computing usage notification is generated based on the planned usage level and the usage measure. The cloud computing usage notification is provided for presentation by an electronic device.

Abstract: A system includes a power disable circuit coupled to a bus connector of a host system and to power circuitry adapted to power on and off a memory device. The power disable circuit includes: source-coupled first FET and second FET with gates to receive a power disable (PWDIS) signal of the bus connector, wherein, in response to an asserted input of the PWDIS signal at a second gate of the second FET, a drain of the first FET is left floating; a latch circuit to assert an output in response to a general purpose input/output signal received from a processing device; and a third FET coupled to the drain of the first FET and to the output of the latch circuit, wherein in response to assertion of the output of the latch circuit, the third FET is to signal to the power circuitry to cut power to the memory device.

Abstract: A semiconductor device includes clock adjustment circuits, provided to a plurality of functional circuits operating in synchronization with a clock signal respectively for adjusting a delay amount for each functional circuit, and a clock path selection circuit for controlling whether a clock is transmitted to the functional circuits through any one of a plurality of paths included in the clock adjustment circuits respectively. In the semiconductor device, the clock path selection circuit outputs a path instruction signal for instructing switching of a path for transmitting a clock signal in accordance with a change in an operation state of a plurality of functional circuits.

Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.

Abstract: A BIOS may include a plurality of protocol drivers and a protocol notification manager configured to receive a protocol notification registration from a consumer driver of the plurality of protocol drivers, receive a unique key associated with the consumer driver, receive a pre-authorized list from a producer driver of the plurality of protocol drivers, the pre-authorized list comprising one or more signed consumer identifiers, each of the one or more signed consumer identifiers identifying a respective one of the plurality of protocol drivers authorized to receive a protocol notification from the producer driver, determine if the unique key successfully decrypts a signed consumer identifier associated with the consumer driver, and perform access control of protocol notification from the producer driver to the consumer driver based on whether the unique key successfully decrypts the signed consumer identifier associated with the consumer driver.

Abstract: A memory device executes a method of controlling power of the memory device. The memory device includes a host interface which receives a command from a host and controls an access to the memory device by the host, a register which is accessible by the host and includes a plurality of different regions, a memory access monitor which monitors which region of the plurality of regions the host accesses, and in response thereto generates a monitoring signal, and a power control manager which selects a power-up group of modules of the memory device in accordance with the monitoring signal and which supplies power to the selected power-up group of modules while not supplying power to any modules of the memory device not belonging to the selected power-up group.

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

Abstract: A Ton/2 generator retrofits a digital tracking algorithm to an analog Constant-On-Time (COT) Controller to enable fast sensing. The Ton/2 generation is cognizant of the delay between high-side switch (HSFET) on generation and the actual turn-on time of the HSFET so that there is no deviation of sampling point, and current is reported with high accuracy. The digital tracking algorithm automatically takes higher steps during load transients to enable faster tracking and scales the measured current (Ipeak/2) based on a discontinuous conduction mode (DCM) period for DCM current reporting.

Abstract: A system, topology, and methods for multiplexing a plurality of POE ports at a POE switch via a single standard wired connection to the downstream where the multiplexed signals and power may be demultiplexed to a plurality of ports.