Abstract: A pixel array may include a group of time-of-flight (ToF) sensors. The pixel array may include an image sensor comprising a group of pixel sensors. The image sensor may be arranged among the group of ToF sensors such that the image sensor is adjacent to each ToF sensor in the group of ToF sensors.

Abstract: A boiling plate including a first surface and a second surface. The first surface provided for contacting a heated component. The second surface is opposite the first surface, and the second surface provided for contacting a liquid medium. The second surface has multiple cone-shaped cavities including a first cone-shaped cavity and a second cone-shaped cavity. A distance between an axis of the first cone-shape cavity and an axis of the second cone-shaped cavity of the multiple cone-shaped cavities are separated by a minimum spacing of four times a radius of the first cone-shaped cavity or the second cone-shaped cavity.

Abstract: A tunneling device includes a first semiconductor portion disposed on a first oxide substrate, a second semiconductor portion disposed on the first semiconductor portion, and an intermediate layer disposed between the first semiconductor portion and second semiconductor portion. The intermediate layer is a natural oxide film obtained by naturally oxidizing one surface of the second semiconductor portion for a predetermined time.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The fin has a wide portion and a width-transition portion. The width-transition portion tapers away from the wide portion in a top view of the substrate, and a first top surface of the wide portion is higher than a second top surface of the width-transition portion. The semiconductor device structure includes a gate stack wrapped around the wide portion. The semiconductor device structure includes a dielectric dummy gate wrapped around the width-transition portion.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a first oxide; a first conductor and a second conductor over the first oxide; a first insulator over the first conductor; a second insulator over the second conductor; a second oxide provided over the first oxide and being in contact with the side surface of the first conductor and the side surface of the second conductor; a third oxide provided over the second oxide and including regions in contact with the side surface of the first insulator and the side surface of the second insulator; a third insulator over the third oxide; and a third conductor over the third insulator.

Abstract: The present application relates to an LED epitaxial structure and the preparation method and application thereof. The LED epitaxial structure comprises a first multiple-quantum-well light-emitting layer and a second multiple-quantum-well light-emitting layer. The first multiple-quantum-well light-emitting layer comprises a first shoes layer, a first well layer, a first cap layer, and a first Barrier layer epitaxially grown from bottom to top in sequence. The second multiple-quantum-well light-emitting layer comprises a second shoes layer, a second well layer, a second cap layer, and a second Barrier layer epitaxially grown from bottom to top in sequence. The technical solutions disclosed in the present application can solve the problem that the 365 nm to 375 nm wave band LED would emit yellow light.

Abstract: A device includes a first vertical stack of nanostructures over a substrate, a second vertical stack of nanostructures over the substrate, a wall structure between and in direct contact with the first and second vertical stacks, a gate structure wrapping around three sides of the nanostructures and a source/drain region beside the first vertical stack of nanostructures.

Abstract: The photoelectric conversion device includes a semiconductor layer provided with an avalanche photodiode, and an interconnection structure layer provided on a side of a first surface of the semiconductor layer. The interconnection structure layer includes an interconnection structure made of a metal material and overlapping with the avalanche multiplication region of the avalanche photodiode in a plan view. The interconnection structure includes a first interconnection, a second interconnection disposed farther from the first surface than the first interconnection, and a contact electrode electrically connecting the first interconnection and the second interconnection. An opening is provided in the first interconnection in a portion overlapping with the avalanche multiplication region in the plan view. The second interconnection is disposed so as to overlap an entire of the opening in the plan view. The contact electrode is arranged around the opening in the plan view.

Abstract: A bonding method for an electronic element includes attaching a solder film to a display substrate and covering multiple bonding pads, performing a heat treatment step so that a solder layer on the multiple bonding pads is transformed into multiple solder bumps, providing at least one electronic element and covering the solder bumps, and heating the solder bumps to electrically bond the at least one electronic element and the bonding pads. The display substrate includes multiple display panels, a first adhesive layer, and a glass cover. The first adhesive layer and the glass cover are disposed on one side of the display panel away from the bonding pads. During the bonding process of the at least one electronic element and the bonding pads, no pressure is applied between the at least one electronic element and the bonding pads.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.

Abstract: The present disclosure relates to an image sensor having an epitaxial deposited photodiode structure surrounded by an isolation structure, and an associated method of formation. In some embodiments, a first epitaxial deposition process is performed to form a first doped EPI layer over a substrate. The first doped EPI layer is of a first doping type. Then, a second epitaxial deposition process is performed to form a second doped EPI layer on the first doped photodiode layer. The second doped EPI layer is of a second doping type opposite from the first doping type. Then, an isolation structure is formed to separate the first doped EPI layer and the second photodiode as a plurality of photodiode structures within a plurality of pixel regions. The plurality of photodiode structures is configured to convert radiation that enters from a first side of the image sensor into an electrical signal.

Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one cationic surfactant having at least one nitrogen atom in the molecule. The slurry includes at least one liquid carrier, at least one abrasive and at least one pH adjusting agent, and has a pH of less than 7.0. The polishing method includes using the slurry composition with the cationic surfactant to polish a conductive layer. The integrated circuit comprises a block layer comprising the cationic surfactant between a sidewall of the conductive plug and an interlayer dielectric layer.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A semiconductor device including a cell active pattern; a cell gate structure connected to the cell active pattern; a peripheral active pattern; a peripheral gate structure connected to the peripheral active pattern; a conductive pattern connected to the peripheral active pattern, the cell gate structure, or the peripheral gate structure; a capacitor structure electrically connected to the cell active pattern; an interlayer insulating layer surrounding the capacitor structure; and a peripheral contact connected to the conductive pattern while extending through the interlayer insulating layer, wherein the interlayer insulating layer includes a first material layer contacting the capacitor structure, and a second material layer on the first material layer, the peripheral contact includes a first portion contacting the first material layer, and a second portion contacting the second material layer, and a maximum width of the first portion is greater than a minimum width of the second portion.

Abstract: There is provided a technique that includes forming a film on a substrate by performing a cycle a predetermined number of times, the cycle including: (a) supplying a precursor gas from a precursor gas supply line into a process chamber in which the substrate is accommodated; and (b) supplying a reaction gas into the process chamber in which the substrate is accommodated, wherein in (a), the precursor gas is divisionally supplied to the substrate a first plural number of times, the precursor gas is pre-filled in a storage installed in the precursor gas supply line and then supplied into the process chamber when the precursor gas is supplied for the first time, and an inside of the process chamber is exhausted before supplying the precursor gas for the second time.

Abstract: The distance between an upper end of a light-shielding portion and a photoelectric conversion layer is longer than the distance between the lower surface of a light-shielding film and the photoelectric conversion layer. The distance between a lower end of the light-shielding portion and the photoelectric conversion layer is shorter than the distance between the lower surface of the light-shielding film and the photoelectric conversion layer. In a plane including the light-shielding film and the light-shielding portion, an opening defined by the light-shielding portion and a gap between the light-shielding portion and the light-shielding film are provided, and the width of the gap is smaller than the width of the opening.

Abstract: An electronic device includes: a substrate including a first region and a second region, wherein the first region is in a middle position, and the second region is closer to an edge of the substrate than the first region; a first active layer disposed on the substrate and in the second region; a conducting electrode disposed on the substrate and in the second region, wherein the conducting electrode electrically connects to the first active layer and extends along a first direction; and a conductive layer disposed on the substrate and in the second region, wherein the conductive layer includes an opening, wherein a minimum distance from an edge of the opening to the first active layer along the first direction is different from a minimum distance from another edge of the opening to the first active layer along a second direction different from the first direction.

Abstract: The present disclosure relates to an image sensor having an epitaxial deposited photodiode structure surrounded by an isolation structure, and an associated method of formation. In some embodiments, a first epitaxial deposition process is performed to form a first doped EPI layer over a substrate. The first doped EPI layer is of a first doping type. Then, a second epitaxial deposition process is performed to form a second doped EPI layer on the first doped EPI layer. The second doped EPI layer is of a second doping type opposite from the first doping type. Then, an isolation structure is formed to separate the first doped EPI layer and the second doped EPI layer as a plurality of photodiode structures within a plurality of pixel regions. The plurality of photodiode structures is configured to convert radiation that enters from a first side of the image sensor into an electrical signal.

Abstract: A light emitting display device includes a substrate, an organic layer, a conductor, an anode, and a pixel definition layer. The organic layer overlaps the substrate and has a connection opening. The conductor is positioned between the substrate and the organic layer. The anode is positioned on the organic layer and is partially positioned inside the connection opening. The pixel definition layer exposes an exposed portion of the anode. The organic layer has a halftone exposure portion and a neighboring portion. The halftone exposure portion overlaps the exposed portion of the anode and overlaps the conductor. The neighboring portion neighbors the halftone exposure portion. A face of the halftone exposure portion and a face of the neighboring portion are spaced from the substrate by a first distance and a second distance, respectively. A difference between the first distance and the second distance is 30 nm or less.