Patents Examined by Jay C. Kim
  • Patent number: 10804272
    Abstract: A semiconductor device capable of retaining data for a long time is provided. A leakage current path between adjacent memory cells in a memory cell array included in the semiconductor device is blocked without increasing the number of manufacturing steps, so that memory retention characteristics can be improved.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: October 13, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Miki Suzuki
  • Patent number: 10790426
    Abstract: A method of manufacturing a light emitting element mounting base member includes: arranging a plurality of core members each including an electrical conductor core and a light-reflecting insulating member provided on a surface of the electrical conductor core; integrally holding the core members with a light blocking resin; and partially removing the insulating members such that at least one surface of the electrical conductor cores is exposed from the light blocking resin.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: September 29, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Yukitoshi Marutani
  • Patent number: 10784303
    Abstract: A CMOS image sensor includes a semiconductor substrate, a plurality of pixel regions in the semiconductor substrate, a deep trench disposed between two adjacent pixel regions and filled with a polysilicon layer doped a first conductivity type, a plurality of well regions having a second conductivity type in each of the pixel regions, a through hole connected to the polysilicon material, and an metal interconnect layer connected to the through hole. The deep trench filled with the doped polysilicon layer completely isolates adjacent pixel regions. A voltage applied to the metal interconnect layer extracts excess photoelectrons generated by intensive incident light to improve the performance of the CMOS image sensor.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 22, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Fugang Chen, Wenlei Chen, Jie Ru
  • Patent number: 10782396
    Abstract: Systems and methods are provided for tracking moving objects from a set of measurements. An estimate of a posterior probability distribution for a plurality of track states is determined from an estimate of the posterior probability distribution for a plurality of possible assignments of the set of measurements to a set of tracks representing trajectories of the plurality of moving objects and the set of measurements. A new estimate of the posterior probability distribution for the assignments is determined from the measurements and the estimate of a posterior probability distribution for the track states. A variational lower bound is determined from the new estimate of the posterior probability distribution for the assignments, the estimate of the posterior probability distribution for the track states, and the set of measurements. These steps are iteratively repeated until the variational lower bound is less than a threshold value.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: September 22, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Ryan D. Turner, Steven Bottone, Bhargav R. Avasarala, Clay J. Stanek
  • Patent number: 10770506
    Abstract: In at least one embodiment, the method is designed for producing a light-emitting diode display (1). The method comprises the following steps: •A) providing a growth substrate (2); •B) applying a buffer layer (4) directly or indirectly onto a substrate surface (20); •C) producing a plurality of separate growth points (45) on or at the buffer layer (4); •D) producing individual radiation-active islands (5), originating from the growth points (45), wherein the islands (5) each comprise an inorganic semiconductor layer sequence (50) with at least one active zone (55) and have a mean diameter, when viewed from above onto the substrate surface (20), between 50 nm and 20 ?m inclusive; and •E) connecting the islands (5) to transistors (6) for electrically controlling the islands (5).
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: September 8, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Norwin Von Malm, Martin Mandl, Alexander F. Pfeuffer, Britta Goeoetz
  • Patent number: 10727355
    Abstract: A semiconductor device includes first and second insulators over a substrate, a semiconductor over the second insulator, first and second conductors over the semiconductor, a third insulator over the semiconductor, a fourth insulator over the third insulator, a third conductor over the fourth insulator, and a fifth insulator over the first insulator, the first conductor and the second conductor. The semiconductor includes first, second, and third regions. The first region overlaps with the third conductor with the third insulator and the fourth insulator positioned therebetween. The second region overlaps with the third conductor with the first conductor, the fourth insulator, and the fifth insulator positioned therebetween. The third region overlaps with the third conductor with the second conductor, the fourth insulator, and the fifth insulator positioned therebetween. The fourth insulator is in contact with a side surface of the fifth insulator in a region overlapping with the semiconductor.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: July 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10720412
    Abstract: Each of a plurality of light emitting elements has a polygonal shape with five or more corners. An interior angle at each of the corners is less than 180°. The plurality of light emitting elements include a first light emitting element having a first bottom surface, a first top surface opposite to the first bottom surface, and a first lateral side surface between the first bottom surface and the first top surface. The second light emitting element has a second bottom surface, a second top surface opposite to the second bottom surface, and a second lateral side surface between the second bottom surface and the second top surface. The second lateral side surface is provided not to oppose to the first lateral side surface in substantially parallel.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: July 21, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Masaki Hayashi, Yuki Shiota, Junya Narita, Keisuke Kurashita, Takanori Akaishi
  • Patent number: 10707369
    Abstract: An avalanche photodiode according to the present invention includes, inside a substrate semiconductor layer having a first conductivity type and a uniform impurity concentration, a first semiconductor layer having the first conductivity type, a second semiconductor layer having a second conductivity type, a third semiconductor layer having the second conductivity type, a fourth semiconductor layer having the second conductivity type, a fifth semiconductor layer having the first conductivity type and formed at a position away from the third semiconductor layer in a lateral direction, a sixth semiconductor layer having the second conductivity type, a first contact, and a second contact. The first semiconductor layer is positioned just under the second semiconductor layer and the fifth semiconductor layer in contact therewith. An avalanche phenomenon is caused at a junction between the first semiconductor layer and the second semiconductor layer.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: July 7, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kazuhiro Natsuaki, Takahiro Takimoto, Masayo Uchida
  • Patent number: 10707305
    Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: July 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Guo Chen, Kun-Yuan Wu, Tai-You Chen, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo
  • Patent number: 10707299
    Abstract: The silicon carbide substrate includes a first impurity region, a second impurity region, and a third impurity region. The first impurity region includes: a first region in contact with the second impurity region; a second region that is in contact with the first region, that is located opposite to the second impurity region when viewed from the first region, and that has an impurity concentration higher than an impurity concentration of the first region; and a third region that is in contact with the second region, that is located opposite to the first region when viewed from the second region, and that has an impurity concentration lower than the impurity concentration of the second region. The gate insulating film is in contact with the first region, the second impurity region, and the third impurity region at a side portion of a trench.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: July 7, 2020
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hiromu Shiomi
  • Patent number: 10685888
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A disposable gate contacts the at least one semiconductor fin. A spacer is disposed on the at least one semiconductor fin and in contact with the disposable gate. Epitaxially grown source and drain regions are disposed at least partially within the at least one semiconductor fin. A first one of silicide and germanide is disposed on and in contact with the source region. A second one of one of silicide and germanide is disposed on and in contact with the drain region. The method includes epitaxially growing source/drain regions within a semiconductor fin. A contact metal layer contacts the source/drain regions. One of a silicide and a germanide is formed on the source/drain regions from the contact metal layer prior to removing the disposable gate.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: June 16, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Hemanth Jagannathan, Christian Lavoie, Ahmet S. Ozcan
  • Patent number: 10680044
    Abstract: A display apparatus includes a first substrate including an active area, a circuit area extending outwardly from the active area, and a cell seal area extending outwardly from the circuit area, a second substrate covering the first substrate, a sealing portion between the first substrate and the second substrate, the sealing portion covering at least a portion of the circuit area, a circuit line in the circuit area of the first substrate and electrically connected to a device in the active area of the first substrate, at least a portion of the sealing portion being on the circuit line, and a pixel definition layer between the sealing portion and the circuit line.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: June 9, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jaekyung Go, Eunjae Na, Minjun Jo, Hyunjun Choi
  • Patent number: 10680001
    Abstract: In the non-volatile semiconductor memory device, a mobile charge collector layer, a mobile charge collecting contact, a mobile charge collecting first wiring layer, an in-between contact between the mobile charge collector layers, and a mobile charge collecting second wiring layer are disposed adjacent to a floating gate. Thereby, without increasing areas of active regions in the non-volatile semiconductor memory device, the number of mobile charges collected near the floating gate is reduced. The non-volatile semiconductor memory device allows high-speed operation of a memory cell while reducing fluctuations in a threshold voltage of the memory cell caused by collection of the mobile charges, which are attracted from an insulation layer, near the floating gate.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: June 9, 2020
    Assignee: FLOADIA CORPORATION
    Inventors: Yasuhiro Taniguchi, Yasuhiko Kawashima, Hideo Kasai, Yutaka Shinagawa, Ryotaro Sakurai, Kosuke Okuyama
  • Patent number: 10665798
    Abstract: A method for manufacturing a semiconductor device includes forming a dielectric layer on a substrate, forming a first carbon nanotube (CNT) layer on the dielectric layer at a first portion of the device corresponding to a first doping type, forming a second CNT layer on the dielectric layer at a second portion of the device corresponding to a second doping type, forming a plurality of first contacts on the first CNT layer, and a plurality of second contacts on the second CNT layer, performing a thermal annealing process to create end-bonds between the plurality of the first and second contacts and the first and second CNT layers, respectively, depositing a passivation layer on the plurality of the first and second contacts, and selectively removing a portion of the passivation layer from the plurality of first contacts.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Shu-Jen Han, Jianshi Tang
  • Patent number: 10665799
    Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer on a substrate, forming a carbon nanotube (CNT) layer on the first dielectric layer, forming a second dielectric layer on the carbon nanotube (CNT) layer, patterning a plurality of trenches in the second dielectric layer exposing corresponding portions of the carbon nanotube (CNT) layer, forming a plurality of contacts respectively in the plurality of trenches on the exposed portions of the carbon nanotube (CNT) layer, performing a thermal annealing process to create end-bonds between the plurality of the contacts and the carbon nanotube (CNT) layer, and depositing a passivation layer on the plurality of the contacts and the second dielectric layer.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Shu-Jen Han, Jianshi Tang
  • Patent number: 10651238
    Abstract: Multi-time programmable (MTP) random access memory (RRAM) devices and methods for forming a MTP RRAM device are disclosed. The method includes providing a substrate. The substrate is prepared with at least a first region for accommodating one or more multi-programmable based resistive random access memory (RRAM) cell. A fin-type based selector is provided over the substrate in the first region. A storage element of the RRAM cell is formed over the fin-type based selector. The fin-type based selector is coupled in series with the storage element of the RRAM cell.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Xuan Anh Tran, Eng Huat Toh
  • Patent number: 10644210
    Abstract: A method of manufacturing a light emitting element mounting base member includes: providing a first insulating member in a plate shaped having at least one recess portion or at least one through-hole; disposing in the recess portion or in the through-hole a light blocking resin and a plurality of core members each equipped with a second insulating member having light reflectivity on each surface of a plurality of electrical conductor cores; and exposing at least one of the surface of the electrical conductor cores from the second insulating members by removing each part of at least one of the second insulating members.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 5, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Yukitoshi Marutani
  • Patent number: 10613956
    Abstract: A terminal device, a system, and a method for efficiently processing sensor data streams. The system for processing sensor data streams includes: at least one data collection unit for receiving the sensor data streams from at least one terminal device; and an allocation unit for monitoring a status of the at least one data collection unit, selecting one of the at least one data collection unit by using a monitoring result, and allocating the at least one terminal device to the selected data collection unit, wherein the at least one data collection unit receives the sensor data streams from the at least one terminal device allocated by the allocation unit.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: April 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hae-dong Yeo
  • Patent number: 10600878
    Abstract: A semiconductor structure is provided including a strained silicon germanium alloy fin that can be employed as a channel material for a FinFET device and having a gate spacer including a lower portion that fills in a undercut region that lies adjacent to the strained silicon germanium alloy fin and beneath raised source/drain (S/D) structures and silicon pedestal structures that can provide improved overlay capacitance.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10600882
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, and an interlayer dielectric disposed on the substrate which has agate structure therein. The gate structure further includes a gate electrode with a protruding portion, and a gate dielectric layer disposed between the gate electrode and the substrate. A spacer is disposed between the interlayer dielectric and the gate electrode. An insulating cap layer is disposed atop the gate electrode and encompasses the top and the sidewall of the protruding portion.
    Type: Grant
    Filed: October 11, 2015
    Date of Patent: March 24, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Wei Chen, Chun-Hsien Lin