Abstract: A method of production of a field-effect transistor from a stack of layers forming a semiconductor-on-insulator type substrate, the stack including a superficial layer of an initial thickness, made of a crystalline semiconductor material and covered with a protective layer, the method including: defining, by photolithography, a gate pattern in the protective layer; etching the gate pattern into the superficial layer to leave a thickness of the layer of semiconductor material in place, the thickness defining a height of a conduction channel of the field-effect transistor; forming a gate in the gate pattern; forming, in the superficial layer and on either side of the gate, source and drain zones, while preserving, in the zones, the initial thickness of the superficial layer.

Abstract: A light emitting element mounting base member for mounting a light emitting element is provided that includes electrical conductor cores, light-reflecting insulating members, and light blocking resin. The insulating members each cover a lateral surface of each of the electrical conductor cores. The insulating members have a reflectivity of 70% or more to light emission wavelength of the light emitting element in a range of 440 nm to 630 nm. The light blocking resin joins at least two insulating members, and is capable of blocking light from the light emitting element by reflecting or absorbing the light. At least one upper surface of the electrical conductor cores, at least one lower surface of the electrical conductor cores are exposed from the insulating members and the light blocking resin respectively.

Abstract: The present invention discloses a method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz: sequentially growing, on a silicon substrate, an N-polar GaN buffer layer, a carbon doped semi-insulated N-polar GaN layer, a non-doped N-polar AlGaN layer, a non-doped N-polar GaN layer and a non-doped N-polar InGaN thin film to obtain a rectifier epitaxial wafer; preparing a pattern groove for a schottky contact electrode on the GaN rectifier epitaxial wafer, and depositing the schottky contact electrode in the groove; preparing a pattern for an ohmic contact electrode, and depositing a device ohmic contact electrode on the surface of the epitaxial wafer; subsequently, depositing a silicon nitride passivation layer at a part where there is no electrode on the surface of the epitaxial wafer, and preparing a surface electrode area; and finally, performing mesa isolation treatment on the GaN rectifier epitaxial wafer.

Abstract: A method of making a semiconductor structure can include: (i) forming a plurality of oxide layers on a semiconductor substrate; (ii) forming a plurality of conductor layers on the plurality of oxide layers; (iii) forming plurality of thickening layers on the plurality of conductor layers; (iv) patterning the plurality of conductor layers and the plurality of thickening layers to form a hard mask; and (v) implanting ion using the hard mask to form a plurality of doped regions.

Abstract: According to an embodiment, a device comprises a direct conversion compound semiconductor layer configured to convert high energy radiation photons into an electric current, the direct conversion compound semiconductor layer comprising: a pixel array positioned in the direct conversion compound semiconductor layer, including pixels located at an outermost circumference, wherein the pixels comprise signal pads; a guard ring encircling the pixel array, wherein the pixels at the outermost circumference are closest to the guard ring; guard ring contact pads, wherein the guard ring contact pads are situated in place of some of the pixel signal pads at the outermost circumference and connected to the guard ring; wherein the guard ring contact pads are further situated asymmetrically with respect to a symmetry x-axis and a symmetry y-axis of the direct conversion compound semiconductor layer.

Abstract: A semiconductor device includes a semiconductor layer over a substrate; a gate insulating film covering the semiconductor layer; a gate wiring including a gate electrode, which is provided over the gate insulating film and is formed by stacking a first conductive layer and a second conductive layer; an insulating film covering the semiconductor layer and the gate wiring including the gate electrode; and a source wiring including a source electrode, which is provided over the insulating film, is electrically connected to the semiconductor layer, and is formed by stacking a third conductive layer and a fourth conductive layer. The gate electrode is formed using the first conductive layer. The gate wiring is formed using the first conductive layer and the second conductive layer. The source electrode is formed using the third conductive layer. The source wiring is formed using the third conductive layer and the fourth conductive layer.

Abstract: A nonvolatile memory device includes a gate line extending in a first horizontal direction; a gate electrode of a pillar shape extending in a vertical direction from the gate line; a plurality of bit lines and a plurality of source lines extending in parallel in a second horizontal direction perpendicular to the first horizontal direction, the plurality of bit lines and the plurality of source lines being stacked in the vertical direction; and a plurality of cell transistors vertically stacked to surround an outer side surface of the gate electrode between the plurality of bit lines and the plurality of source lines. Each of the cell transistors includes a gate dielectric layer which surrounds the outer side surface of the gate electrode and a channel layer which surrounds an outer side surface of the gate dielectric layer.

Abstract: A method of manufacturing a light emitting element mounting base member includes: providing a first insulating member in a plate shaped having at least one recess portion or at least one through-hole; disposing in the recess portion or in the through-hole a light blocking resin and a plurality of core members each equipped with a second insulating member having light reflectivity on each surface of a plurality of electrical conductor cores; and exposing at least one of the surface of the electrical conductor cores from the second insulating members by removing each part of at least one of the second insulating members.

Abstract: A normally-off electronic device, comprising: a semiconductor body including a heterostructure that extends over a buffer layer; a recessed-gate electrode, extending in a direction orthogonal to the plane; a first working electrode and a second working electrode at respective sides of the gate electrode; and an active area housing, in the on state, a conductive path for a flow of electric current between the first and second working electrodes. A resistive region extends at least in part in the active area that is in the buffer layer and is designed to inhibit the flow of current between the first and second working electrodes when the device is in the off state. The gate electrode extends in the semiconductor body to a depth at least equal to the maximum depth reached by the resistive region.

Abstract: The present disclosure includes a substrate, a moisture-transmission delay part, and a protective layer. The substrate includes a display area, and a non-display area disposed outside the display area. The moisture-transmission delay part includes a trench which is formed to surround the display area and which has a cross section in which a lower portion has a width greater than a width of an upper portion. The protective layer covers the display area and the non-display area in which the moisture-transmission delay part is formed.

Abstract: Vertically stacked memory devices and methods of manufacture are provided. The structures include a substrate stack including a first row of horizontal electrodes disposed over a first insulating layer and first insulating layer disposed over a substrate. The substrate stack further includes a second row of horizontal electrodes separated from the first row of horizontal electrodes by a second insulating layer, and the first row of horizontal electrodes is form over and substantially parallel to the second row of horizontal electrodes. A third insulating layer is formed over the second row of horizontal electrodes. A plurality of vertical gate trenches formed through the third insulating layer, the second row of horizontal electrodes, the second insulating layer, the first row of horizontal electrodes and the first insulating layer. The plurality of vertical gate trenches filled with a layer of channel material, a layer of electrolyte material and filled with a metal.

Abstract: It is an object to provide a semiconductor device with less power consumption as a semiconductor device including a thin film transistor using an oxide semiconductor layer. It is an object to provide a semiconductor device with high reliability as a semiconductor device including a thin film transistor using an oxide semiconductor layer. In the semiconductor device, a gate electrode layer (a gate wiring layer) intersects with a wiring layer which is electrically connected to a source electrode layer or a drain electrode layer with an insulating layer which covers the oxide semiconductor layer of the thin film transistor and a gate insulating layer interposed therebetween. Accordingly, the parasitic capacitance formed by a stacked-layer structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer can be reduced, so that low power consumption of the semiconductor device can be realized.

Abstract: A semiconductor device includes a thin film transistor, wherein: a semiconductor layer of the thin film transistor has a layered structure including a lower oxide semiconductor layer including In, Ga, Zn and Sn and an upper oxide semiconductor layer arranged on the lower oxide semiconductor layer and including In, Ga and Zn; a thickness of the lower oxide semiconductor layer is 20 nm or less; an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer is 5% or more; the upper oxide semiconductor layer includes no Sn, or an atomic ratio of Sn with respect to all metal elements of the upper oxide semiconductor layer is smaller than an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer; and a first angle ?1 between a side surface and a lower surface of the lower oxide semiconductor layer is smaller than a second angle ?2 between a side surface and a lower surface of the upper oxide semiconductor layer.

Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. The semiconductor device includes an oxide semiconductor; a second insulator; a first conductor and a first insulator that are embedded in the second insulator; a second conductor; a third conductor; and a third insulator covering the oxide semiconductor. The oxide semiconductor includes a region where an angle formed between a plane that is parallel to a bottom surface of the oxide semiconductor and the side surface of the oxide semiconductor is greater than or equal to 30° and less than or equal to 60°.

Abstract: A semiconductor device of the present invention includes a semiconductor layer, a gate trench that defines a source region of a first conductivity type in the semiconductor layer, a channel region of a second conductivity type of a lower part of the source region, a source trench that passes through the source region and the channel region, an impurity region of the second conductivity type of a bottom part and a side part of the source trench, a source electrode on the semiconductor layer, and a highly-concentrated impurity region of the second conductivity type, the highly-concentrated impurity region having a contact portion connected to the source electrode at a surface of the semiconductor layer, the highly-concentrated impurity region passing through the source region and extending to a position deeper than the source region, the highly-concentrated impurity region having a concentration higher than the impurity region.

Abstract: Provided is a photo-detection device including: a semiconductor substrate having a first face; a pixel unit in which a pixel having an avalanche diode is arranged in the semiconductor substrate; and a sixth semiconductor region arranged so as to surround a first semiconductor region to a fifth semiconductor region that form the avalanche diode in a planar view from a direction perpendicular to the first face, and an electric potential that is different from the electric potential supplied to the avalanche diode is supplied to the sixth semiconductor region.

Abstract: It is an object to provide a semiconductor device with less power consumption as a semiconductor device including a thin film transistor using an oxide semiconductor layer. It is an object to provide a semiconductor device with high reliability as a semiconductor device including a thin film transistor using an oxide semiconductor layer. In the semiconductor device, a gate electrode layer (a gate wiring layer) intersects with a wiring layer which is electrically connected to a source electrode layer or a drain electrode layer with an insulating layer which covers the oxide semiconductor layer of the thin film transistor and a gate insulating layer interposed therebetween. Accordingly, the parasitic capacitance formed by a stacked-layer structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer can be reduced, so that low power consumption of the semiconductor device can be realized.

Abstract: An object of the invention is to improve the reliability of a light-emitting device. Another object of the invention is to provide flexibility to a light-emitting device having a thin film transistor using an oxide semiconductor film. A light-emitting device has, over one flexible substrate, a driving circuit portion including a thin film transistor for a driving circuit and a pixel portion including a thin film transistor for a pixel. The thin film transistor for a driving circuit and the thin film transistor for a pixel are inverted staggered thin film transistors including an oxide semiconductor layer which is in contact with a part of an oxide insulating layer.

Abstract: Systems, apparatuses, and methods related to atom implantation for passivation of pillar material are described. An example apparatus includes a pillar of a semiconductor device. The pillar may include a first portion (e.g., a passivation material) formed from silicon nitride and an underlying second portion formed from a conductive material. A region of the first portion opposite from an interface between the first portion and the underlying second portion may be implanted with atoms of an element different from silicon (Si) and nitrogen (N) to enhance passivation of the implanted region.

Abstract: A high-voltage termination for a semiconductor device includes a substrate of a first conductivity type, an implanted device region of a second conductivity type of the semiconductor device, a shallow trench disposed in the substrate adjacent to the implanted device region, a doped extension region of the second conductivity type extending between the implanted device region and a first edge of the shallow trench adjacent to the implanted device region, a junction termination extension region of the second conductivity type formed in the shallow trench contacting the extension region and extending past a second edge of the shallow trench opposite the implanted device region, an insulating layer formed over at least a portion of the extension region and over the junction termination extension region, and a metal layer formed over the insulating layer extending into at least a portion of the shallow trench and electrically connected to the extension region.